AD9863 datasheet(32/40 Pages) AD

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AD9863

Rev. A| Page 32 of 40

Description

Bit 4: TxPGA Fast Update (Mode)

The TxPGA fast bit controls the update speed of the TxPGA. When fast update mode is enabled, the

TxPGA provides fast gain settling within a few clock cycles, which may introduce spurious signals at

the output of the Tx path. The default setting for this bit is low, and the TxPGA gives a smooth

transition between gain settings. Fast mode is enabled when this bit is set high.

Bit 7: Tx Twos Complement

The default data format for Tx data is straight binary. Set this bit high when providing twos

complement Tx data.

Bit 6: Rx Twos Complement

The default data format for Rx data is straight binary. Set this bit high when providing twos

complement Rx data.

Bit 5: Tx Inverse Sample

By default, the transmit data is sampled on the rising edge of the CLKOUT. Setting this bit high

changes this, and the transmit data are sampled on the falling edge.

Bit 1, Bit 0: Interpolation Control

These register bits control the interpolation rate of the transmit path. The default settings are both

bits low, indicating that both interpolation filters are bypassed. The MSB and LSB are Address Bit 1

and Address Bit 0, respectively. Setting binary 01 provides an interpolation rate of 2×; binary 10

provides an interpolation rate of 4×.

Bit 5: Dig Loop On

When enabled, this bit enables a digital loop-back mode. The digital loop-back mode provides a

means of testing digital interfaces and functionality at the system level. In digital loop-back mode,

the full-duplex interface must be enabled. (Refer to the Flexible I/O Interface Options section.) The

device accepts data from the digital input bus according to the FD mode timing, and the data is

processed by using the Tx digital path (including any enabled interpolation filter). The processed

data is then output from the Rx path bus.

Bit 4: SPIFD/HD

Control bit to configure full-duplex (high) or half-duplex (low) interface mode. This register, in

combination with the SpiB12/24 register, configures the interface mode of FD, HD12, or HD24. The

device is in FD mode.

Bit 3: SpiTx/Rx

Control bit for transmit or receive mode for the half-duplex clock modes. High represents Tx and

low represents Rx.

Bit 2: SpiB12/24

Control bit for 12-bit or 24-bit modes. High represents 12-bit mode and low represents 24-bit mode.

Bit 1: SPI IO Control

Use in conjunction with SpiTx/Rx [Register14, Bit 3] to override external Tx/Rx pin operation.

Bit 0: SpiClone

Set high when in clone mode (see Flexible I/O Interface Options section for definition of clone

mode). Clk_mode should also be set to Binary 111, such as [Register 01[7:5] = 111.

Bit 7: PLL_Bypass

Setting this bit high bypasses the PLL. When bypassed, the PLL remains active.

Bit 5: ADC Clock Div

By default the ADCs are driven directly from CLKIN1 in normal timing operation or from the PLL

output clock in the alternative timing operation. This bit is used to divide the source of the ADC

clock prior to the ADCs. The default setting is low and performs no division. Setting this bit high

divides the clock by 2.

Bit 4: Alt Timing Mode

Table 5 describes two timing modes: the normal timing operation mode and the alternative timing

operation mode. The default configuration is normal timing mode, and the CLKIN1 drives the Rx

path. In alternative timing mode, the PLL output is used to drive the Rx path. The alternative

operation mode is configured by setting this bit high.

Bit 3: PLL Div5

The output of the PLL can be divided by 5 by setting this bit high. By default, the PLL directly drives

the Tx digital path with no division of its output.

Bit 2 to Bit 0: PLL Multiplier

These bits control the PLL multiplication factor. A default setting is Binary 000, which configures the

PLL to 1× multiplication factor. This register, in combination with the PLL Div5 register, sets the PLL

output frequency. The programmable multiplication factors are

000

1×

001

2×

010

4×

011

8×

100

16×

101 to 111

not used

Bit 5: PLL to IFACE2

Setting this bit high switches the IFACE2 output signal to the PLL output clock. It is valid only if

Bit 2: PLL Slow

Changes the PLL loop bandwidth; changes profile of the phase noise generated from the PLL clock.

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