AD9863

Rev. A | Page 29 of 40

SPI Register Map

Registers 0x00 to 0x29 of the AD9863 provide flexible operation of the device. The SPI allows access to many configurable options.

Detailed descriptions of the bit functions are found in Table 17.

Table 16. Register Map

Reg. Name

Reg.

Add

7

6

5

4

3

2

1

0

General

0x00

SDIO BiDir

LSB first

Soft reset

Clock Mode

0x01

clk_mode [2:0]

Enable

IFACE2

clkout

Inv clkout

(IFACE3)

Power-Down

0x02

Tx analog

Tx digital

Rx digital

PLL power-

down

PLL output

disconnect

RxA Power-

Down

0x03

Rx_A analog

Rx_A DC bias

RxB Power-

Down

0x04

Rx_B analog

Rx_B DC bias

Rx Power-

Down

0x05

Rx analog bias

RxRef

DiffRef

VREF

Rx Path

0x06

Rx_A twos

complement

Rx_A Clk

Duty

Rx Path

0x07

Rx_B twos

complement

Rx_B Clk

Duty

Rx Path

0x08

Rx ultralow

power

control

Rx ultralow

power

control

Rx path

0x09

Rx ultralow

power control

Rx ultralow

power control

Rx ultralow

power

control

Rx Path

0x0A

Rx ultralow

power control

Rx ultralow

power control

Rx ultralow

power

control

Tx Path

0B

DAC A offset [9:2]

Tx Path

0C

DAC A offset [1:0]

DAC A offset

direction

Tx Path

0D

DAC A coarse gain control

DAC A fine gain [5:0]

Tx Path

0E

DAC B offset [9:2]

Tx Path

0F

DAC B offset [1:0]

DAC B offset

direction

Tx Path

10

DAC B coarse gain control

DAC B fine gain [5:0]

Tx Path

11

TxPGA gain [7:0]

Tx Path

12

TxPGA slave

enable

TxPGA fast

update

I/O

Configuration

13

Tx twos

complement

Rx twos

complement

Tx inverse

sample

Interpolation control [1:0]

I/O

Configuration

14

Dig loop on

SpiFD/HD

Spi

Tx/Rx

SpiB12/24

SPI IO

control

SpiClone

Clock

15

PLL bypass

ADC clock div

Alt timing

mode

PLL Div5

PLL multiplier [2:0]

Clock

16

PLL to IFACE2

PLL slow