AD9863 datasheet(38/40 Pages) AD

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AD9863

Rev. A| Page 38 of 40

Table 22. Serial Registers Related to the Clock Distribution Block

Bit(s)

Function

Enable IFACE2 clkout

0: There is no clock output from IFACE2 pin, except in FD mode.

1: The IFACE2 pin outputs a continuous reference clock from the PLL output. In FD mode,

this inverts the IFACE2 output.

Inv clkout (IFACE3)

0: The IFACE3 clock output is not inverted.

1: The IFACE3 clock output is inverted.

Tx Inverse Sample

0: The Tx path data is latched relative to the output Tx clock rising edge.

1: The Tx path data is latched relative to the output Tx clock falling edge.

Interpolation Control

Sets interpolation of 1×, 2×, or 4× for the Tx path.

PLL_Bypass

0: PLL block is used to generate system clock.

1: PLL block bypasses generate system clock.

ADC Clock Div

0: ADC clock rate equals the Rx path frequency.

1: ADC clock is one-half the Rx path frequency.

Alt Timing Mode

0: CLKIN1 is used to drive the Rx path clock.

1: PLL block output is used to drive the Rx path clock.

PLL Div5

0: PLL block output clock is not divided down.

1: PLL block output clock is divided by 5.

PLL Multiplier

Sets multiplication factor of the PLL block to 1× (000), 2× (001), 4× (010), 8× (011), or 16x (100).

PLL to IFACE2

0: If enable IFACE2 clkout register is set, IFACE2 outputs buffered CLKIN.

1: If enable IFACE2 clkout register is set, IFACE2 outputs buffered PLL output clock.

Transmit (Tx) timing requires specific setup and hold times to

properly latch data through the data interface bus. These timing

parameters are specified relative to an internally generated

output reference clock. The AD9863 has two interface clocks

provided through the IFACE3 and IFACE2 pins. The transmit

timing specifications and setup and hold times provide a

minimum required window of valid data.

Setup time (tSETUP) is the time required for data to initially settle

to a valid logic level prior to the relative output timing edge.

Hold time (tHOLD) is the time after the output timing edge that

valid data must remain on the data bus to be properly latched.

Figure 59 shows tSETUP and tHOLD relative to IFACE3 falling edge.

Note that in some cases negative time is specified, for example,

with tHOLD timing, which means that the hold time edge occurs

before the relative output clock edge.

IFACE3 (CLKOUT)

Tx DATA

tSETUP

tHOLD

Figure 59. Tx Data Timing Diagram

Table 23 shows typical setup and hold times for the AD9863 in

the various mode configurations.

Table 23. Typical Tx Data Latch Timing Relative to

IFACE3 Falling Edge

Mode No.

Mode Name

tSETUP (ns)

tHOLD (ns)

–2.5

Optional FD

–2.5

HD24

–1.5

Optional HD24

–1.5

HD12

–2.5

Optional HD12

–2.5

Clone

–1.5

Receive (Rx) path data is output after a reference output clock

edge. The time delay of the Rx data relative to a reference

output clock is called the output delay, tOD. The AD9863 has two

possible interface clocks provided through the IFACE3 and

IFACE2 pins. Figure 60 shows tOD relative to the IFACE3 rising

edge. Note that in some cases negative time is specified, which

means that the output data transition occurs prior to the relative

output clock edge.

IFACE3 (CLKOUT)

Rx DATA

tOD

Figure 60. Rx Data Timing Diagram

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