AD9863 datasheet(23/40 Pages) AD

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AD9863

Rev. A | Page 23 of 40

DIGITAL BLOCK

Flexible I/O Interface Options

The AD9863 digital block allows the device to be configured

in various timing and operation modes. The following sec-

tions discuss the flexible I/O interfaces, the clock distribution

block, and the programming of the device through mode pins

or SPI registers.

The AD9863 can accommodate various data interface transfer

options (flexible I/O). The AD9863 uses two 12-bit buses, an

upper bus (U12) and a lower bus (L12), to transfer the dual-

channel 12-bit ADC data and dual-channel 12-bit DAC data by

means of interleaved data, parallel data, or a mix of both. Table 10

shows the different I/O configurations of the modes depending

on half-duplex or full-duplex operation. Table 11 and Table 12

summarize the pin configurations vs. the modes.

Table 10. Flexible Data Interface Modes

Mode

Name

Tx Only Mode (Half-Duplex)

Rx Only Mode (Half-Duplex)

Concurrent Tx + Rx Mode

(Full-Duplex)

General Notes

HD24

U[0:11]

DIGITAL

BACK

END

AD9863

Tx_A DATA

03604-0-078

L[0:11]

Tx_B DATA

IFACE1

Tx/Rx

IFACE2

OUTPUT CLOCK

IFACE3

OUTPUT CLOCK

L[0:11]

DIGITAL

BACK

END

AD9863

Rx_A DATA

03604-0-082

Rx_B DATA

U[0:11]

IFACE1

Tx/Rx

IFACE2

OUTPUT CLOCK

IFACE3

OUTPUT CLOCK

N/A

Rx data rate

= 1 × ADC sample rate

Two 12-bit parallel Rx data

buses

Tx data rate

= 1 × ADC sample rate

Two 12-bit parallel Tx data

buses

HD12

U[0:11]

DIGITAL

BACK

END

AD9863

Tx_A/B DATA

03604-0-079

L[11]

TxSYNC

IFACE1

Tx/Rx

IFACE2

OUTPUT CLOCK

IFACE3

OUTPUT CLOCK

U[11]

DIGITAL

BACK

END

AD9863

RxSYNC

03604-0-083

Rx_A/B DATA

L[0:11]

IFACE1

Tx/Rx

IFACE2

OUTPUT CLOCK

IFACE3

OUTPUT CLOCK

N/A

Rx data rate

= 2 × ADC sample rate

One 12-bit interleaved Rx

data bus

Tx data rate

= 2 × ADC sample rate

One 12-bit interleaved Tx

data bus

U[0:11]

DIGITAL

BACK

END

AD9863

Tx_A/B DATA

03604-0-080

L[0:11]

IFACE1

TxSYNC

IFACE2

OUTPUT CLOCK

IFACE3

OUTPUT CLOCK

U[0:11]

DIGITAL

BACK

END

AD9863

03604-0-084

Rx_A/B DATA

L[0:11]

IFACE1

IFACE2

OUTPUT CLOCK

IFACE3

OUTPUT CLOCK

U[0:11]

DIGITAL

BACK

END

AD9863

Tx_A/B DATA

03604-0-086

Rx_A/B DATA

L[0:11]

IFACE1

TxSYNC

IFACE2

OUTPUT CLOCK

IFACE3

OUTPUT CLOCK

Rx data rate

= 2 × ADC sample rate

One 12-bit interleaved Rx

data bus

Tx data rate

= 2 × ADC sample rate

One 12-bit interleaved Tx

data bus

Clone

U[0:11]

DIGITAL

BACK

END

AD9863

Tx_A/B DATA

03604-0-081

TxSYNC

L[11]

IFACE1

Tx/Rx

IFACE2

OUTPUT CLOCK

IFACE3

OUTPUT CLOCK

U[0:11]

DIGITAL

BACK

END

AD9863

Rx_A DATA

03604-0-085

Rx_B DATA

L[0:11]

IFACE1

Tx/Rx

IFACE2

OUTPUT CLOCK

IFACE3

OUTPUT CLOCK

N/A

Rx data rate

= 1 × ADC sample rate

Two 12-bit parallel Rx data

buses

Tx data rate

= 2 × ADC sample rate

One 12-bit interleaved Tx

data bus

Requires SPI interface to

configure; similar to AD9862

data interface

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