AD9863 datasheet(30/40 Pages) AD

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AD9863

Rev. A| Page 30 of 40

Table 17. Register Bit Descriptions

Description

Bit 7: SDIO BiDir (Bidirectional)

Default setting is low, which indicates that the SPI serial port uses dedicated input and output lines

(4-wire interface), SDIO pins and SDO pins, respectively. Setting this bit high configures the serial

port to use the SDIO pin as a bidirectional data pin.

Bit 6: LSB First

Default setting is low, which indicates MSB first SPI port access mode. Setting this bit high

configures the SPI port access to LSB first mode.

Bit 5: Soft Reset

Writing a high to this register resets all the registers to their default values and forces the PLL to

relock to the input clock. The soft reset bit is a one-shot register and is cleared immediately after

the register write is completed.

Bit 7 to Bit 5: Clk_Mode

These bits represent the clocking interface for the various modes. Setting 000 is default. Setting 111

is used for clone mode. Refer to the Summary of Flexible I/O Modes section for a definition of clone

mode.

Setting

Mode

000

Standard FD, HD12, HD24 Clock (Modes 1, 4, 7)

001

Optional FD timing (Mode 2)

010

Not used

011

Optional HD24 timing (Mode 5)

100

Not used

101

Optional HD12 timing (Mode 8)

110

Not used

111

Clone Mode (Mode 10)

Bit 2: Enable IFACE2 clkout

Enables the IFACE2 port to be an output clock. Also inverts the IFACE2 output clock in full-duplex mode.

Bit 1: Inv clkout (IFACE3)

Inverts the output clock on IFACE3.

Bit 7 to Bit 5: Tx Analog

(Power-Down)

Three options are available to reduce analog power consumption for the Tx channels. The first two

options disable the analog output from Tx Channel A or B independently, and the third option

disables the output of both channels and reduces the power consumption of some of the addi-

tional analog support circuitry for maximum power savings. With all three options, the DAC bias

current is not powered down, so recovery times are fast (typically a few clock cycles). The list below

explains the different modes and settings used to configure them.

Power-down option bits setting [7:5]

Power-down Tx A channel analog output [1 0 0]

Power-down Tx B channel analog output [0 1 0]

Power-down Tx A and Tx B analog outputs [1 1 1]

Bit 4: Tx Digital (Power-Down)

Default is low, which enables the digital section of the transmit path to operate as programmed

through other registers. By setting this bit high, the digital blocks are not clocked to reduce power

consumption. When enabled, the Tx outputs are static, holding their last update values.

Bit 3: Rx Digital (Power-Down)

Setting this bit high powers down the digital section of the receive path of the chip. Typically, any

unused digital blocks are automatically powered down.

Bit 2: PLL Power-Down

Setting this register bit high forces the CLKIN2 PLL multiplier to a power-down state. This mode can

be used to conserve power or to bypass the internal PLL. To operate the AD9863 when the PLL is

bypassed, CLKIN2 must be supplied with a clock equal to the fastest Tx path clock.

Bit 1: PLL Output Disconnect

Setting this register bit high disconnects the PLL output from the clock path. If the PLL is enabled, it

locks or stays locked as normal.

Bit 7: Rx_A Analog/

Rx_B Analog (Power-Down)

Either ADC or both ADCs can be powered down by setting the appropriate register bit high. The

entire analog circuitry of the Rx channel is powered down, including the differential references,

input buffer, and the internal digital block. The band gap reference remains active for quick

recovery.

Bit 6: Rx_A DC Bias/

Rx_B DC Bias (Power-Down)

Setting either of these bits high powers down the input common-mode bias network for the

respective channel and requires an input signal to be properly dc-biased. By default, these bits are

low, and the Rx inputs are self-biased to approximately AVDD/2 and accept an ac-coupled input.

Bit 7: Rx Analog Bias (Power-

Down)

Setting this bit high powers down all analog bias circuits related to the receive path (including the

differential reference buffer). Because bias circuits are powered down, there is an additional power

saving, but also a longer recovery time relative to other Rx power-down options.

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