AD9863

Rev. A | Page 39 of 40

Table 24 shows typical output delay times for the AD9863 in the various mode configurations.

Table 24. AD9863 Rx Data Latch Timing

Mode No.

Mode Name

Relative to:

1

FD

+2.5 ns

Relative to IFACE2 rising edge

+1 ns

Relative to IFACE3 rising edge

2

Optional FD

+1 ns

Relative To IFACE3 rising edge

+2 ns

IFACE2 (RxSYNC) relative to LSB

4

HD24

−1.5 ns

Relative to IFACE3 rising edge

5

Optional HD24

−0.5 ns

Relative to IFACE3 rising edge

7

HD12

−1.5 ns

Relative to IFACE3 rising edge

8

Optional HD12

+0.5 ns

Relative to IFACE3 rising edge

+0 ns

U12 (RxSYNC) relative to LSB

10

Clone

+1.5 ns

Relative to IFACE3 rising edge

Configuration Without Serial Port Interface (Using Mode Pins)

The AD9863 can be configured using mode pins if a serial port interface is not available. This section applies only to configuring the

AD9863 without an SPI. Refer to the Configuring with Mode Pins section of the data sheet for more information.

When using the mode pin option, the pins shown in Table 25 are used to configure the AD9863.

Table 25. Using Mode Pin (SPI Disabled) to Configure Timing (SPI_CS, Pin 64, Must be Tied Low)

Clock Mode

Interpolation

Setting

PLL Setting

FD/HD

Pin 3

12/20

Pin 17

Interp1, Interp0

Pin 1, Pin 2

Mode 1 (FD)

2×

4×

2×

4×

1

N/A1

0, 1

1, 0

Mode 4 (HD24)

1×

2×

4×

Bypassed

2×

4×

0

0

0, 0

0, 1

1, 0

Mode 7 (HD12)

2×

4×

2×

4×

0

1

0, 1

1, 0