AD9863 datasheet(31/40 Pages) AD

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AD9863

Rev. A | Page 31 of 40

Description

Bit 6: RxREF (Power-Down)

Setting this register bit high powers down internal ADC reference circuits. Powering down these

circuits provides additional power saving over other power-down modes. The Rx path wake-up

time depends on the recovery of these references, typically of the order of a few milliseconds.

Bit 5: DiffRef (Power-Down)

Setting this bit high powers down the ADC’s differential references, REFT and REFB. Recovery time

depends on the value of the REFT and REFB decoupling capacitors.

Bit 4: VREF (Power-Down)

Setting this register bit high powers down the ADC reference circuit, VREF. Powering down the Rx

band gap reference allows an external reference to drive the VREF pin setting full-scale range of the

Rx paths.

Registers 0x06/0x07: Rx Path

Bit 5: Rx_A Twos Complement/

Rx_B Twos Complement

Default data format for the Rx data is straight binary. Setting this bit high generates twos

complement data.

Bit 4: Rx_A Clk Duty/Rx_B Clk

Duty

Setting either of these bits high enables the respective channels of the on-chip duty cycle stabilizer

(DCS) circuit to generate the internal clock for the Rx block. This option is useful for adjusting for

high speed input clocks with skewed duty cycles. The DCS mode can be used with ADC sampling

frequencies over 40 MHz.

Registers 0x08/0x09/0x0A: Rx Path

Rx Ultralow Power Control Bits

Set all bits high, in combination with asserting the ADC_LO_PWR pin, to reduce the power

consumption of the Rx path by a fourth of normal Rx path power consumption.

Registers 0x0B/0x0C/0x0E/0x0F:

Tx Path

DAC A/DAC B Offset

These 10-bit, twos complement registers control a dc current offset that is combined with the Tx A

or Tx B output signal. An offset current of up to ±12% IOUTFS (2.4 mA for a 20 mA full-scale output)

can be applied to either differential pin on each channel. The offset current can be used to

compensate for offsets that are present in an external mixer stage, reducing LO leakage at its

output. The default setting is 0x00, no offset current. The offset current magnitude is set by using

the lower nine bits. Setting the MSB high adds the offset current to the selected differential pin,

while setting the MSB low subtracts the offset value.

DAC A/DAC B Offset Direction

This bit determines to which differential output pin the offset current is applied for the selected

channel. Setting this bit low applies the offset to the negative differential pin. Setting this bit high

applies the offset to the positive differential pin.

Bit 7, Bit 6: DAC A/DAC B Coarse

Gain Control

These register bits scale the full-scale output current (IOUTFS) of either Tx channel independently.

IOUT of the Tx channels is a function of the RSET resistor, the TxPGA setting, and the coarse gain

control setting.

Output current scaling by 1/11

Output current scaling by ½

No output current scaling

Bit 5 to Bit 0: DAC A/DAC B Fine

Gain

The DAC output curve can be adjusted fractionally through the gain trim control. Gain trim of up to

±4% can be achieved on each channel individually. The gain trim register bits are a twos

complement attention control word.

MSB, LSB

100000

Maximum positive gain adjustment

111111

Minimum positive gain adjustment

000000

No adjustment (default)

000001

Minimum negative gain adjustment

011111

Maximum negative gain adjustment

Bit 0 to Bit 7: TxPGA Gain

This 8-bit, straight binary (Bit 0 is the LSB, Bit 7 is the MSB) register control for the Tx programmable

gain amplifier (TxPGA). The TxPGA provides a 20 dB continuous gain range with 0.1 dB steps (linear

in dB) simultaneously to both Tx channels. By default, this register setting is 0xFF.

MSB, LSB

0000 0000

Minimum gain scaling –20 dB

1111 1111

Maximum gain scaling 0 dB

Bit 6: TxPGA Slave Enable

The TxPGA gain is controlled through register TxPGA gain setting and, by default, is updated

immediately after the register write. If this bit is set, the TxPGA gain update is synchronized with the

falling edge of a signal applied to the TxPwrDwn pin and is enabled during the wake-up from

power-down.

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