AD9863 datasheet(18/40 Pages) AD

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AD9863

Rev. A| Page 18 of 40

THEORY OF OPERATION

SYSTEM BLOCK

The AD9863 is targeted to cover the mixed-signal front end

needs of multiple wireless communications systems. It features

a receive path that consists of dual 12-bit receive ADCs and a

transmit path that consists of dual 12-bit transmit DACs

(TxDAC). The AD9863 integrates additional functionality

typically required in most systems, such as power scalability,

Tx gain control, and clock multiplication circuitry.

The AD9863 minimizes both size and power consumption to

address the needs of a range of applications from the low power

portable market to the high performance base station market.

The part is provided in a 64-lead lead frame chip scale package

(LFCSP) that has a footprint of only 9 mm × 9 mm. Power

consumption can be optimized to suit the particular application

beyond just a speed grade option by incorporating power-down

controls, low power ADC modes, TxDAC power scaling, and a

half-duplex mode, which automatically disables the unused

digital path.

The AD9863 uses two 12-bit buses to transfer Rx path data and

Tx path data. These two buses support 24-bit parallel data

transfers or 12-bit interleaved data transfers. The bus is

configurable through either external mode pins or internal

registers settings. The registers allow many more options for

configuring the entire device.

The following sections discuss the various blocks of the AD9863:

Rx Path Block, Tx Path Block, Digital Block, Programmable

Registers, and Clock Distribution Block.

Rx PATH BLOCK

Rx Path General Description

The AD9863 Rx path consists of two 12-bit, 50 MSPS analog-

to-digital converters (ADCs). The dual ADC paths share the

same clocking and reference circuitry to provide optimal

matching characteristics. Each of the ADCs consists of a 9-stage

differential pipelined switched capacitor architecture with

output error correction logic.

The pipelined architecture permits the first stage to operate on a

new input sample, while the remaining stages operate on

preceding samples. Sampling occurs on the falling edge of the

input clock. Each stage of the pipeline, excluding the last,

consists of a low resolution flash ADC and a residual multiplier

to drive the next stage of the pipeline. The residual multiplier

uses the flash ADC output to control a switched capacitor

digital-to-analog converter (DAC) of the same resolution. The

DAC output is subtracted from the stage’s input signal, and the

residual is amplified (multiplied) to drive the next pipeline

stage. The residual multiplier stage is also called a multiplying

DAC (MDAC). One bit of redundancy is used in each stage to

facilitate digital correction of flash errors. The last stage simply

consists of a flash ADC.

The differential input stage is dc self-biased and allows

differential or single-ended inputs. The output-staging block

aligns the data, carries out the error correction, and passes the

data to the output buffers.

The latency of the Rx path is about 5 clock cycles.

Rx Path Analog Input Equivalent Circuit

The Rx path analog inputs of the AD9863 incorporate a novel

structure that merges the function of the input sample-and-hold

amplifiers (SHAs) and the first pipeline residue amplifiers into a

single, compact switched capacitor circuit. By eliminating one

amplifier in the pipeline, this structure achieves considerable

noise and power savings over a conventional implementation

that uses separate amplifiers.

Figure 46 illustrates the equivalent analog inputs of the AD9863

(a switched capacitor input). Bringing CLK to logic high opens

Switch S3 and closes Switch S1 and Switch S2; this is the sample

mode of the input circuit. The input source connected to VIN+

and VIN− must charge capacitor CH during this time. Bringing

CLK to a logic low opens Switch S2, and then Switch S1 opens,

followed by the closing of Switch S3. This puts the input circuit

into hold mode.

VIN+

RIN

VCM

CIN

RIN

VIN–

–

Figure 46. Differential Input Architecture

The structure of the input SHA places certain requirements on

the input drive source. The differential input resistors are

typically 2 kΩ each. The combination of the pin capacitance,

CIN, and the hold capacitance, CH, is typically less than 5 pF. The

input source must be able to charge or discharge this capaci-

tance to 12-bit accuracy in one-half of a clock cycle. When the

SHA goes into sample mode, the input source must charge or

discharge capacitor CH from the voltage already stored on it to

the new voltage. In the worst case, a full-scale voltage step on

the input source must provide the charging current through the

RON of Switch S1 (typically 100 Ω) to a settled voltage within

one-half of the ADC sample period. This situation corresponds

to driving a low input impedance. On the other hand, when the

source voltage equals the value previously stored on CH, the

hold capacitor requires no input current and the equivalent

input impedance is extremely high.

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