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AD9863 Datasheet(PDF) 34 Page - Analog Devices

Part # AD9863
Description  Mixed-Signal Front-End (MxFE) Baseband Transceiver for Broadband Applications
PDF  40 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9863 Datasheet(HTML) 34 Page - Analog Devices

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AD9863
Rev. A| Page 34 of 40
Write Operations
The SPI write operation uses the instruction header to config-
ure a 1-byte or 2-byte register write using the 2/1 byte setting.
The instruction byte followed by the register data is written
serially into the device through the SDIO pin on rising edges
of the interface clock, SCLK. The data can be transferred MSB
first or LSB first, depending on the setting of the LSB-first
register bit. The write operation is the same, regardless of
SDIO BiDir register setting.
Figure 52 to Figure 54 are examples of writing data into the
device. Figure 52 shows a 1-byte write in MSB-first mode;
Figure 53 shows a 2-byte write in MSB-first mode; and
Figure 54 shows a 2-byte write in LSB-first mode. Note the
differences between LSB- and MSB-first modes: both the
instruction header and data are reversed, and the second data
byte register location is different. In the default MSB-first
mode, the second data byte is written to a decremented
register address. In LSB-first mode, the second data byte is
written to an incremented register address.
INSTRUCTION HEADER
REGISTER DATA
tS
tDS
tDH
tHI
tLO
tCLK
tH
DON'T CARE
DON'T CARE
2/1
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DON'T CARE
DON'T CARE
SEN
SCLK
SDIO
R/W
Figure 52. 1-Byte Serial Register Write in MSB-First Mode
tH
tS
tDS
tDH
tHI
tLO
tCLK
SEN
SCLK
SDIO
DON'T CARE
DON'T CARE
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
2/1
DON'T CARE
DON'T CARE
INSTRUCTION HEADER (REGISTER N)
REGISTER (N) DATA
REGISTER (N–1) DATA
Figure 53. 2-Byte Serial Register Write in MS-First Mode
tH
tS
tDS
tDH
tHI
tLO
tCLK
SEN
SCLK
SDIO
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
INSTRUCTION HEADER (REGISTER N)
REGISTER (N) DATA
REGISTER (N+1) DATA
A0
A1
A2
A3
A4
A5
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
R/W
2/1
Figure 54. 2-Byte Serial Register Write in LSB-First Mode



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