AM79C976 datasheet(24/309 Pages) AMD

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Am79C976

8/01/00

P R E L I M INARY

PIN DESCRIPTIONS

PCI Interface

AD[31:0]

Address and Data

Input/Output

Address and data are multiplexed on the same bus in-

terface pins. During the first clock of a transaction,

AD[31:0] contain a physical address (32 bits). During

the subsequent clocks, AD[31:0] contain data. Byte or-

dering is Little Endian by default. AD[7:0] are defined

as the least significant byte (LSB) and AD[31:24] are

defined as the most significant byte (MSB). For FIFO

data transfers, the Am79C976 controller can be pro-

grammed for Big Endian byte ordering. See Control 0

During the address phase of the transaction, when the

Am79C976 controller is a bus master, AD[31:2] will

address the active Double Word (DWord). The

Am79C976 controller always drives AD[1:0] to “00” dur-

ing the address phase indicating linear burst order.

When the Am79C976 controller is not a bus master, the

AD[31:0] lines are continuously monitored to determine

if an address match exists for slave transfers.

During the data phase of the transaction, AD[31:0] are

driven by the Am79C976 controller when performing

bus master write and slave read operations. Data on

AD[31:0] is latched by the Am79C976 controller when

performing bus master read and slave write operations.

The Am79C976 device supports Dual Address Cycles

(DAC) for systems with 64-bit addressing. As a bus

master the Am79C976 device will generate addresses

of up to 40 bits in length. If the value of the C/BE[3:0]

bus during the PCI address phase is 1101b, the ad-

dress phase is extended to two clock cycles. The low

order address bits appear on the AD[31:0] bus during

the first clock cycle, and the high order bits appear dur-

ing the second clock cycle. In dual address cycles the

PCI bus command (memory read, I/O write, etc.) ap-

pears on the C/BE pins during the second clock cycle.

C/BE[3:0]

Bus Command and Byte Enables

Input/Output

Bus command and byte enables are multiplexed on the

same bus interface pins. During the address phase of

the transaction, C/BE[3:0] define the bus command.

During the data phase, C/BE[3:0] are used as byte en-

ables. The byte enables define which physical byte

lanes carry meaningful data. C/BE0 applies to byte 0

(AD[7:0]) and C/BE3 applies to byte 3 (AD[31:24]). The

function of the byte enables is independent of the byte

ordering mode (BSWP, CSR3, bit 2).

CLK

Clock

Input

This clock is used to drive the system bus interface. All

bus signals are sampled on the rising edge of CLK and

all parameters are defined with respect to this edge.

The Am79C976 controller normally operates over a fre-

quency range of 15 MHz to 33 MHz on the PCI bus due

to networking demands. The Am79C976 controller will

support a clock frequency of 0 MHz after certain pre-

cautions are taken to ensure data integrity. This clock

or a derivation is not used to drive any network func-

tions.

DEVSEL

Device Select

Input/Output

The Am79C976 controller drives DEVSEL when it de-

tects a transaction that selects the device as a target.

The device samples DEVSEL to detect if a target

claims a transaction that the Am79C976 controller has

initiated.

FRAME

Cycle Frame

Input/Output

FRAME is driven by the Am79C976 controller when it

is the bus master to indicate the beginning and duration

of a transaction. FRAME is asserted to indicate a bus

transaction is beginning. FRAME is asserted while

data transfers continue. FRAME is deasserted before

the final data phase of a transaction. When the

Am79C976 controller is in slave mode, it samples

FRAME to determine the address phase of a transac-

tion.

GNT

Bus Grant

Input

This signal indicates that the access to the bus has

been granted to the Am79C976 controller.

The Am79C976 controller supports bus parking. When

the PCI bus is idle and the system arbiter asserts GNT

without an active REQ from the Am79C976 controller,

the device will drive the AD[31:0], C/BE[3:0], and PAR

lines.

IDSEL

Initialization Device Select

Input

This signal is used as a chip select for the Am79C976

controller during configuration read and write transac-

tions.

INTA

Interrupt Request

Output

An attention signal which indicates that one or more

enabled interrupt flag bits are set. See the descriptions

of the INT and INTEN registers for details.

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