AM79C976 datasheet(91/309 Pages) AMD

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Am79C976

P R E L I M INARY

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Receive Frame Tagging is a feature that allows the ex-

ternal address detection logic to pass an identification

code or tag to the Am79C976 controller to be placed in

the RX descriptor corresponding to a received frame.

The external logic can shift this tag in as a serial bit

stream on the Receive Frame Tag Data (RXFRTGD)

pin. It uses the Receive Frame Tag Enable (RXFRTGE)

pin to indicate when the tag data is valid. The clock sig-

nal for shifting in the tag data is RX_CLK. See

Figure 3535.

If the Software Style (SWSTYLE) field in BCR20 con-

tains the value 2 or 3, the Receive Frame Tag can be

up to 15 bits long. In this case the tag data is sampled

on the low-to-high transition of RX_CLK whenever RX-

FRTGE is high. If SWSTLYE = 5, the Receive Frame

Tag can be up to 32 bits long. In this case, the tag data

is sampled on both edges of RX_CLK so that the entire

tag can be shifted in 16 RX_CLK cycles or less, de-

pending on the length of the tag. If SWSTYLE is 0 or 4,

Receive Frame Tagging is not supported. In those

cases the descriptor space is allocated to other func-

tions.

If SWSTYLE = 5, tag bits are shifted in the order B31,

B15, B30, B14, … , B0, where B0 is the least significant

bit of the tag. This sequence allows the external logic

to be simplified slightly if the system design requires a

frame tag of fewer than 17 bits. In this case the external

logic can use only one clock edge to shift in the data.

Since the Am79C976 device samples the RXFRTGD

pin on both edges of RX_CLK, the same data will ap-

pear in the upper and lower halves of the frame tag field

in the descriptor.

If SWSTYLE = 2 or 3, tag bits are shifted in the order

B14, B13, ... , B0.

Because of the order in which frame tag bits are shifted

in, if the tag is shorter than 15 bits, the tag data will be

placed in the least significant portion of the Receive

Frame Tag field of the RX descriptor, and the most sig-

nificant bits of the field will be cleared to zeros.

RXFRTGE need not be a continuous signal. It can tog-

gle on and off so that the tag data can be shifted in at a

slower rate than the frequency of RX_CLK. The length

of the frame tag is determined by the number of

RX_CLK cycles during which RXFRTGE is asserted

before the end of the frame arrives (with a maximum of

15 bits for SWSTYLE 2 or 3 or a maximum of 32 bits for

SWSTYLE 5). The last bit of the Receive Frame Tag

must be shifted into the RXFRTGD input at least one

RX_CLK cycle before RX_DV is de-asserted.

The Receive Frame Tagging feature is enabled by the

RXFRTAGEN bit in the Command1 Register. When this

bit is cleared to 0, the Receive Frame Tag field of the

RX descriptor will be filled with zeros.

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External Memory Interface

The Am79C976 controller contains an External Mem-

ory Interface that supports Flash (or EPROM) devices

as boot devices, as well as SSRAM for frame data stor-

age. The controller provides read and write access to

Flash or EPROM. No glue logic is required for the

memory interface.

The Am79C976 device contains a built-in self test sys-

tem (MBIST) that can be programmed to run a diag-

nostics test on the external SSRAM.

The external SSRAM is organized around a 32-bit data

bus. The memory can be as large as 1M X 32 bits. The

memory devices can be either JEDEC standard Pipe-

line Burst Synchronous Static RAM devices (PB-SS-

RAM) or ZBT™ Synchronous Static RAM (ZBT-

SSRAM) with pipelined outputs. The SRAM_TYPE

field of the Control1 Register must be initialized to

indicate which type of SSRAM is actually used.

RX_CLK

RX_DV

MIIRXFRTGE

MIIRXFRTGD

SF/BD

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