AM79C976 datasheet(37/309 Pages) AMD

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8/01/00

Am79C976

P R E L I M INARY

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The Am79C976 device includes an interface to an op-

tional expansion ROM. The amount of PCI address

space claimed by this ROM is determined by the con-

tents of the ROM Configuration Register, ROM_CFG,

which should normally be loaded from the serial EE-

PROM.

The host must initialize the Expansion ROM Base

Address register at offset 30H in the PCI configuration

space with a valid address before enabling the access

to the device. The Am79C976 controller will not react to

any access to the Expansion ROM until both MEMEN

(PCI Command register, bit 1) and ROMEN (PCI Ex-

pansion ROM Base Address register, bit 0) are set to 1.

After the Expansion ROM is enabled, the Am79C976

controller will assert DEVSEL on all memory read ac-

cesses to the memory space defined by the contents of

the Expansion ROM Base Address register. The

Am79C976 controller aliases all accesses to the Ex-

pansion ROM of the command types Memory Read

Multiple and Memory Read Line to the basic Memory

Read command. Eight-bit, 16-bit, and 32-bit read trans-

fers are supported.

Since setting MEMEN also enables memory mapped

access to the I/O resources, attention must be given

the PCI Memory Mapped I/O Base Address register

before enabling access to the Expansion ROM. The

host must set the PCI Memory Mapped I/O Base Ad-

dress register to a value that prevents the Am79C976

controller from claiming any memory cycles not in-

tended for it.

The Am79C976 controller will always read four bytes

for every host Expansion ROM read access. Since this

takes more than 16 PCI clock cycles, the Am79C976

device will assert STOP to force a PCI bus retry. Sub-

sequent accesses will be retried until all four bytes have

been read from the ROM and stored in an internal tem-

porary register. The timing of the access to the ROM

device is determined by the ROMTMG parameter

(CTRL0, bits 11-8).

Note: The Expansion ROM must not be read when the

Am79C976 controller is running (when the RUN bit in

CMD0 is set to 1). Any access to the Expansion ROM

clears the RUN bit and thereby abruptly stops all net-

work and DMA operations.

When the host tries to write to the Expansion ROM, the

Am79C976 controller will claim the cycle. The write op-

eration will have no effect. Writes to the Expansion

ROM are done through the BCR30 Expansion Bus

Data Port. See the section on the Expansion Bus Inter-

face for more details.

During the boot procedure, the system will try to find an

Expansion ROM. A PCI system assumes that an Ex-

pansion ROM is present when it reads the ROM signa-

ture 55H (byte 0) and AAH (byte 1).

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In addition to the normal completion of a transaction,

there are three scenarios in which the Am79C976 con-

troller terminates a slave access for which it is the tar-

get.

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If a slave access to the Am79C976 device takes more

than 16 PCI CLK cycles, the Am79C976 device will

generate a PCI disconnect/retry cycle by asserting

STOP and deasserting TRDY while keeping DEVSEL

asserted. This will free up the PCI bus so that it can be

used by other bus masters while the Am79C976 device

is busy. See Figure 55.

The Am79C976 controller cannot service any slave ac-

cess while it is reading the contents of the EEPROM.

Simultaneous access is not allowed in order to avoid

conflicts, since the EEPROM is used to initialize some

of the PCI configuration space locations and user-se-

lected BCRs and CSRs. The EEPROM read operation

will always happen automatically following H_RESET.

(See the H_RESET section for more details.) In addi-

tion, the host can start the read operation by setting the

PREAD bit (BCR19, bit 14). While the EEPROM read

is on-going, the Am79C976 controller will disconnect

any slave access where it is the target by asserting

STOP together with DEVSEL, while driving TRDY high.

STOP will stay asserted until the end of the cycle.

Note: The I/O and memory slave accesses will only be

disconnected if they are enabled by setting the IOEN or

MEMEN bit in the PCI Command register. Without the

enable bit set, the cycles will not be claimed at all.

Since H_RESET clears the IOEN and MEMEN bits for

the automatic EEPROM read after H_RESET, the dis-

connect only applies to configuration cycles.

The Am79C976 device will also generate PCI discon-

nect/retry cycles when it is executing a blocking read

access to an external PHY register.

AM79C976 Datasheet(PDF) 37 Page - Advanced Micro Devices

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