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AM79C976 Datasheet(PDF) 95 Page - Advanced Micro Devices |
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AM79C976 Datasheet(HTML) 95 Page - Advanced Micro Devices |
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95 / 309 page  8/01/00 Am79C976 95 P R E L I M INARY )LJXUH )ODVK 5HDGIURP ([SDQVLRQ %XV'DWD 3RUW )LJXUH )ODVK :ULWH6HTXHQFH 65$0 &RQILJXUDWLRQ The Am79C976 controller uses external SSRAM for re- ceive and transmit FIFOs. The size of the SSRAM can be up to 4 Mbytes, organized as 1M X 32 bits. The size of the SSRAM is indicated by the contents of the SSRAM Size Register (or BCR25). SRAM_SIZE should be loaded from the EEPROM. The SSRAM is programmed in units of 512-byte pages. To specify how much of the SSRAM is allocated to transmit and how much is allocated to receive, the user should program SRAM_BND Register (or BCR26, bits 15-0) with the page boundary where the receive buffer begins. The SRAM_BND is also programmed in units of 512-byte pages. The transmit buffer space starts at 0000h. It is up to the user or the software driver to split up the memory for transmit or receive; there is no de- faulted value. The minimum SSRAM size required is four 512-byte pages for each transmit and receive queue, which limits the SSRAM size to be at least 4 Kbytes. The SRAM_BND upon H_RESET will be reset to 0000h. SRAM_BND must be programmed to a non- zero value if the transmitter is enabled. SRAM_BND should be programmed to a value larger than the max- imum frame size to use the automatic retransmission options, REX_UFLO, REX_RTRY, and RTRY_LCOL, or if the transmit FIFO start point, XMTSP, is set to Full Frame. (XMTSP is CTRL1, bits 17-16, or CSR80, bits 11-10.) The Am79C976 controller does not allow software di- agnostic access to the SRAM as do older devices in the PCnet family. The Am79C976 controller provides soft- ware access to an internal memory built-in self-test (MBIST) controller which runs extensive, at-speed ROMCLK ERA[19:0] FLCS FLOE ERD[7:0] FLWE ROMCLK ERA[19:0] FLCS FLOE ERD[7:0] FLWE |
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