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AM79C976 Datasheet(PDF) 57 Page - Advanced Micro Devices |
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AM79C976 Datasheet(HTML) 57 Page - Advanced Micro Devices |
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57 / 309 page  8/01/00 Am79C976 57 P R E L I M INARY )LJXUH'HVFULSWRU 5LQJ:ULWH,Q%XUVW0RGH ),)2 '0$ 7UDQVIHUV Am79C976 logic will determine when a FIFO DMA transfer is required. This transfer mode will be used for transfers of data to and from the Am79C976 FIFOs. Once the Am79C976 BIU has been granted bus mas- tership, it will perform a series of consecutive transfer cycles before relinquishing the bus. All transfers within the master cycle will be either read or write cycles, and all transfers will be transferred to contiguous, ascend- ing addresses. Burst cycles are used whenever possi- ble. A burst transaction will start with an address phase, fol- lowed by one or more data phases. AD[1:0] will always be 0 during the address phase indicating a linear burst order. During FIFO DMA read operations, all byte lanes will always be active. The Am79C976 controller will inter- nally discard unused bytes. During the first and the last data phases of a FIFO DMA burst write operation, one or more of the byte enable signals may be inactive. All other data phases will always write a complete DWord. Figure 26 shows the beginning of a FIFO DMA write with the beginning of the buffer not aligned to a DWord boundary. The Am79C976 controller starts off by writ- ing only three bytes during the first data phase. This op- eration aligns the address for all other data transfers to a 32-bit boundary so that the Am79C976 controller can continue bursting full DWords. GNT REQ DEVSEL TRDY PAR C/BE FRAME CLK 35 PAR AD IRDY DEVSEL is sampled DATA 1 2 4 6 7 8 0110 0000 0011 MD2 PAR DATA PAR 22929B27 |
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