AM79C976 datasheet(88/309 Pages) AMD

88 / 309 page

Am79C976

8/01/00

P R E L I M INARY

For the other style of flow control, a single pause frame

is sent to halt transmissions for a predetermined period

of time. The contents of the request_operand field of

this frame are taken from the Pause Length register.

This style of flow control is selected by setting the Fixed

Length Pause bit (FIXP) to 1.

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The Flow Control pin (FC) allows external hardware to

cause pause frames to be transmitted or back pressure

to be asserted. The use of the FC pin for traffic regula-

tion is enabled by the FC Pin Enable bit (ENFC). When

FCPEN is cleared to 0, the signal on the FC pin is ig-

nored. Otherwise, back pressure is enabled when FC

is high and the device is operating in half-duplex mode,

and pause frames are sent at FC pin signal transitions

when the device is operating in full-duplex mode.

In full-duplex mode with the FC Pin Enable bit (FCPEN)

=1, the actions that occur at low-to-high and high-to-

low transitions of the FC pin depend on the value of the

Fixed Length Pause bit (FIXP). If FIXP is 1, a low-to-

high transition causes a pause frame to be sent with its

request_operand field contents taken from the Pause

Length register. In this case high-to-low transitions of

the FC pin are ignored.

If FIXP is 0, a low-to-high transition sends a pause

frame whose request_operand field contains 0FFFFh,

while a high-to-low transition sends a pause frame

whose request_operand field contains 0.

The effects of the FC pin are summarized in Table 13.

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For software control of traffic regulation the Flow Con-

trol Command bit (FCCMD) mimics the FC pin.

In half-duplex mode, back pressure is enabled when

FCCMD is set to 1, and it is disabled when FCCMD is

cleared to 0.

In full-duplex mode, the act of setting FCCMD to 1

causes a pause frame to be sent. The contents of the

request_operand field of the frame depend on the state

of the FIXP bit. If FIXP is 1, the contents of the

request_operand field are copied from the Pause

Length register. If FIXP is 0, the contents of the

request_operand field are set to 0FFFFh.

In full-duplex mode, if FIXP is 0, the act of clearing

FCCMD to 0 causes a pause frame to be sent with its

request_operand field cleared to 0.

If FIXP is set to 1, the FCCMD bit is self-clearing--the

CPU does not have to write to the Am79C976 device to

clear the FCCMD bit. This allows the CPU to use a sin-

gle write access to cause a pause frame to be sent with

a predetermined request_operand field.

Table 13. FC Pin Functions

FC Pin

Transition

FCPEN FIXP

Duplex

Mode

Action

No Action

0 to 1

Half

Enable back

pressure

1 to 0

Half

Disable back

pressure

0 to 1

Full

Send pause frame

with request

operand equal to

the contents of the

Pause Length

1 to 0

Full

No action

0 to 1

Full

Send pause frame

with request

operand equal to

0FFFFh.

1 to 0

Full

Send pause frame

with request

operand equal to

0000h.

AM79C976 Datasheet(PDF) 88 Page - Advanced Micro Devices

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