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AM79C976 Datasheet(PDF) 41 Page - Advanced Micro Devices |
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AM79C976 Datasheet(HTML) 41 Page - Advanced Micro Devices |
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41 / 309 page  8/01/00 Am79C976 41 P R E L I M INARY Table 3. PCI Commands )LJXUH %XV$FTXLVLWLRQ The Am79C976 controller typically performs more than one non-burst read transaction within a single bus mas- tership period. FRAME is dropped between consecu- tive non-burst read cycles. REQ, however, stays asserted until FRAME is asserted for the last transac- tion. The Am79C976 controller supports zero wait- state read cycles. It asserts IRDY immediately after the address phase and at the same time starts sampling DEVSEL. Figure 11 shows two non-burst read transac- tions. The first transaction has zero wait states. In the second transaction, the target extends the cycle by as- serting TRDY one clock later. %DVLF%XUVW5HDG 7UDQVIHU The Am79C976 controller supports burst mode for all bus master read operations. To allow burst transfers in descriptor read operations, the Am79C976 controller must be programmed to use SWSTYLE 3, 4, or 5 (BCR20, bits 7-0). The BIU chooses which PCI command to use as fol- lows: s When reading one DWord, use Memory Read. s When reading a block of more than one DWord that does not cross a cache line, use Memory Read Line. s When reading a block that crosses a cache line boundary, use Memory Read Multiple. C[3:0] Command Use 0000 Interrupt Acknowledge Not used 0001 Special Cycle Not used 0010 I/O Read Not used 0011 I/O Write Not used 0100 Reserved 0101 Reserved 0110 Memory Read Read of the initialization block and descriptor rings Read of the transmit buffer in non-burst mode 0111 Memory Write Write to the descriptor rings and to the receive buffer 1000 Reserved 1001 Reserved 1010 Configuration Read Not used 1011 Configuration Write Not used 1100 Memory Read Multiple Read of descriptor or transmit buffer in burst mode 1101 Dual Address Cycle Used when required 1110 Memory Read Line Read of descriptor or transmit buffer in burst mode 1111 Memory Write Invalidate Burst write of 1 or more complete cache lines to the receive buffer 22929B12 FRAME CLK AD IRDY C/BE REQ GNT 1 2345 CMD ADDR |
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