AM79C976 datasheet(29/309 Pages) AMD

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Am79C976

P R E L I M INARY

Note: The FLA[23:20] pins are multiplexed with the

ERD[11:8] pins.

ERD[31:0]/FLD[7:0]

External Memory Data [31:0]

Input/Output

The ERD[7:0] pins provide data bits [7:0] for boot ROM

accesses. The ERD[31:0] pins provide data bits [31:0]

for external SSRAM accesses. The ERD[31:0] signals

are forced to a constant level to conserve power while

no access on the External Memory Bus is being per-

formed.

Note: The FLA[23:20] pins are multiplexed with the

ERD[11:8] pins.

ERCE

External SSRAM Chip Enable

Output

ERCE serves as the chip enable for the external SS-

RAM. It is asserted low when the SSRAM address on

the ERA[19:0] pins is valid.

FLCS

Boot ROM Chip Select

Output

FLCS serves as the chip select for the boot device. It is

asserted low when the boot ROM address on the

FLA[23:20] and ERA[19:0] pins is valid.

EROE

External SSRAM Output Enable

Output

EROE is asserted active LOW during SSRAM device

read operations to allow the SSRAM device to drive the

ERD[31:0] data bus. It is deasserted at all other times.

FLOE

Expansion ROM Output Enable

Output

FLOE is asserted active LOW during boot ROM read

operations to allow the boot ROM to drive the ERD[7:0]

data bus. It is deasserted at all other times.

Note: The FLOE pin is multiplexed with the ERADV

pin.

ERWE/FLWE

External Memory Write Enable

Output

ERWE provides the write enable for write accesses to

the external SSRAM and the Flash (boot ROM) device.

ERADSP/CEN

External Memory Address Strobe

Output

ERADSP provides the address strobe signal to load

the address into the external SSRAM.

ERADV

External Memory Address Advance

Output

ERADV provides the address advance signal to the ex-

ternal SSRAM. This signal is asserted low during a

burst access to increment the address counter in the

SSRAM.

Note: The FLOE pin is multiplexed with the ERADV

pin.

ERCLK

External Memory Clock

Output

ERCLK is the reference clock for all synchronous

SRAM accesses.

Media Independent Interface

TX_CLK

Transmit Clock

Input

TX_CLK is a continuous clock input that provides the

timing reference for the transfer of the TX_EN and

TXD[3:0] signals out of the Am79C976 device.

TX_CLK must provide a nibble rate clock (25% of the

network data rate). Hence, an MII transceiver operating

at 10 Mbps must provide a TX_CLK frequency of 2.5

MHz and an MII transceiver operating at 100 Mbps

must provide a TX_CLK frequency of 25 MHz.

TXD[3:0]

Transmit Data

Output

TXD[3:0] is the nibble-wide MII transmit data bus. Valid

data is generated on TXD[3:0] on every TX_CLK rising

edge while TX_EN is asserted. While TX_EN is deas-

serted, TXD[3:0] values are driven to a 0. TXD[3:0]

transitions synchronous to TX_CLK rising edges.

TX_EN

Transmit Enable

Output

TX_EN indicates when the Am79C976 device is pre-

senting valid transmit nibbles on the MII. While TX_EN

is asserted, the Am79C976 device generates TXD[3:0]

on TX_CLK rising edges. TX_EN is asserted with the

first nibble of preamble and remains asserted through-

out the duration of a packet until it is deasserted prior

to the first TX_CLK following the final nibble of the

frame. TX_EN transitions synchronous to TX_CLK ris-

ing edges.

COL

Collision

Input

COL is an input that indicates that a collision has been

detected on the network medium.

CRS

Carrier Sense

Input

CRS is an input that indicates that a non-idle medium,

due either to transmit or receive activity, has been de-

tected.

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