AM79C976 datasheet(74/309 Pages) AMD

74 / 309 page

Am79C976

8/01/00

P R E L I M INARY

rectly into PCI memory space and can not be accessed

indirectly through the RAP and RDP registers.

To simplify the use of software debuggers, the counter

logic is designed so that the statistics counters can be

accessed one, two, or four bytes at a time. When a por-

tion of a statistics counter is read, the entire 32 bits of

the counter is loaded into an internal holding register in

a single atomic operation. When the CPU reads one or

more bytes from the same counter, the data are read

from the holding register rather than from the counter.

The holding register is updated when either a read ac-

cess is made to a different counter or a byte of the

same counter is read for a second time.

Write access to statistics counters is provided for de-

bugging purposes only. No holding register is used for

write accesses. Writing one or two bytes at a time to a

statistics counter while the network is active can cause

unpredictable results.

The contents of the entire set of statistics counters can

be cleared to zero by setting the INIT_MIB bit (CMD3,

bit 25). The counters will be cleared within approxi-

mately 55 ERCLK cycles after the INIT_MIB bit is set.

5HFHLYH 6WDWLVWLFV &RXQWHUV

The receive statistics counters are defined and the

Management Information Base (MIB) objects that they

support are listed in Table 7.

For these counters, the definition of a valid frame de-

pends on the state of the JUMBO and VSIZE bits

(CMD3, bits 21 and 20) as follows:

If JUMBO = 1, valid frames are frames that are be-

tween 64 and 65536 bytes in length and have a correct

FCS value. Frames longer than 65536 bytes may not

be handled properly.

If JUMBO = 0 and VSIZE = 0, valid frames are frames

that are between 64 and 1518 bytes in length and have

a correct FCS value.

If JUMBO = 0 and VSIZE = 1, valid frames are frames

that are between 64 and 1522 bytes in length and have

a correct FCS value.

In Table 7, the Offset column gives the offset with re-

spect to the value stored in the read-only MIB Offset

address space allocated to the Am79C976 device. The

actual address of a particular counter is the sum of the

following quantities:

7KH FRQWHQWV RI WKH 3&, 0HPRU\0DSSHG ,2 %DVH

$GGUHVV 5HJLVWHU

7KH FRQWHQWV RI WKH 0,% 2IIVHW5HJLVWHU

7KH RIIVHWJLYHQ LQ7DEOH

Table 7. Receive Statistics Counters

Offset (hex)

Receive Counter Name

MIB Object Supported

Description of Counter/Comments

RcvMissPkts

RMON etherStatsDropEvents

RMON etherHistoryDropEvents

MIB-II ifInDiscards

E-like

dot3StatsInternalMacReceiveErrors

The number of times a receive packet was

dropped due to lack of resources. This is

the number of times a packet was dropped

due to receive FIFO overflow. This count

does not include undersize, oversize,

misaligned or bad FCS packets.

RcvOctets

RMON etherStatsOctets

RMON etherHistoryOctets

MIB-II IfInOctets

The total number of octets of data

received including octets from invalid

frames. This does not include the

preamble but does include the FCS bits.

The RcvOctets counter is incremented

whenever the receiver receives an octet.

RcvBroadCastPkts

RMON etherStatsBroadcastPkts

RMON etherHistoryBroadcastPkts

EXT-MIB-II ifInBroadcastPkts

The total number of valid frames received

that are addressed to a broadcast

address. This counter does not include

errored broadcast packets or valid

multicast packets.

RcvMultiCastPkts

RMON etherStatsMulticastPkts

RMON etherHistoryMulticastPkts

EXT-MIB-II ifInMulticastPkts

The total number of valid frames received

that are addressed to a multicast address.

This counter does not include errored

multicast packets or valid broadcast

packets.

AM79C976 Datasheet(PDF) 74 Page - Advanced Micro Devices

AM79C976 Datasheet(HTML) 74 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL