AM79C976 datasheet(27/309 Pages) AMD

27 / 309 page

8/01/00

Am79C976

P R E L I M INARY

This pin can drive the external system management

logic that causes the CPU to get out of a low power

mode of operation. This pin is implemented for designs

that do not support the PME function.

Three bits that are loaded from the EEPROM into

CSR116 can program the characteristics of this pin:

1. RWU_POL determines the polarity of the RWU sig-

nal.

2. If RWU_GATE bit is set, RWU is forced to the high

impedance state when PG input is LOW.

3. RWU_DRIVER determines whether the output is

open drain or totem pole.

The internal power-on-reset signal forces this output

into the high impedance state until after the polarity and

drive type have been determined.

WUMI

Wake-Up Mode Indicator

Output,

Open Drain

This output, which is capable of driving an LED, is as-

serted when the device is in Magic Packet mode. It can

be used to drive external logic that switches the device

power source from the main power supply to an auxil-

iary power supply.

VAUX_SENSE

3.3 Vaux Presence Sense

Input

The signal on this pin is logically anded with bit 15 of

the PCI PMC register when the PMC register is read.

This pin should normally be connected to the PCI

3.3 Vaux pin. This allows the PMC register to indicate

that the device is capable of supporting PME from the

D3cold state only when the 3.3 Vaux pin is supplying

power.

CLKSEL0

Clock Select 0

Input

The Am79C976 system clock can either be driven by

an external clock generator connected to the XCLK pin

or by an internal clock generator timed by a 25-MHz

crystal connected between the XTAL1 and XTAL2 pins.

The CLKSEL0 and CLKSEL1 pins select the source of

the system clock and the frequency at which the exter-

nal clock generator must run. In addition, CLKSEL0

and CLKSEL1 determine the frequency of ERCLK, the

external SSRAM clock. Table 1 shows the possible

combinations.

CLKSEL1

Clock Select 1

Input

The Am79C976 system clock can either be driven by

an external clock generator connected to the XCLK pin

or by an internal clock generator timed by a 25-MHz

crystal connected between the XTAL1 and XTAL2 pins.

The CLKSEL0 and CLKSEL1 pins select the source of

the system clock and the frequency at which the exter-

nal clock generator must run. In addition CLKSEL0 and

CLKSEL1 determine the frequency of ERCLK, the ex-

ternal SSRAM clock. Table 1 shows the possible com-

binations.

CLKSEL2

Clock Select 2

Input

The CLKSEL2 pin must be held low during normal op-

eration.

TEST

Test Reset

Input

The TEST pin must be held low during normal opera-

tion.

XCLK

External Clock Input

Input

The Am79C976 system clock can either be driven by

an external clock generator connected to this pin or by

a 25-MHz crystal connected between the XTAL1 and

XTAL2 pins, depending on the state of the CLKSEL0

an d CLKSEL1 pins. When either CL KSEL0 or

CLKSEL1 or both are held high, a 20-, 25-, or

3-MHz clock signal must be applied to XCLK as

shown in Table 1. When CLKSEL0 and CLKSEL1 are

both held low, the XCLK pin should be connected to ei-

ther VSS or VDD.

Table 1. System Clock Selections

XTAL1

Crystal

Input

If the CLKSEL0 and CLKSEL1 pins are both held low,

a 25-MHz crystal should be connected between the

XTAL1 pin and the XTAL2 pin. This crystal controls the

frequency of the internal clock-generator circuit.

If the CLKSEL0 and CLKSEL1 pins are not both held

low, a 20-, 25-, or 331/

3-MHz clock source must be con-

CLKSEL2 CLKSEL1 CLKSEL0

CLOCK

SOURCE

ERCLK

(MHz)

Design Factory

Test Only.

000

25-MHz

Crystal,

XTAL1,XT

AL2

87.5

001

XCLK, 20

MHz

010

XCLK, 25

MHz

87.5

011

XCLK,

331/

3 MHz

82.5

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