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AM79C976 Datasheet(PDF) 52 Page - Advanced Micro Devices |
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AM79C976 Datasheet(HTML) 52 Page - Advanced Micro Devices |
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52 / 309 page  52 Am79C976 8/01/00 P R E L I M INARY )LJXUH 0DVWHU &\FOH'DWD 3DULW\ (UURU 5HVSRQVH Whenever the Am79C976 controller is the current bus master and a data parity error occurs, SINT (CSR5, bit 11) will be set to 1. When SINT is set, INTA is asserted if the enable bit SINTE (CSR5, bit 10) is set to 1. This mechanism can be used to inform the driver of the sys- tem error. The host can read the PCI Status register to determine the exact cause of the interrupt. The setting of SINT due to a data parity error is not dependent on the setting of PERREN (PCI Command register, bit 6). By default, a data parity error does not affect the state of the MAC engine. The Am79C976 controller treats the data in all bus master transfers that have a parity error as if nothing has happened. All network activity contin- ues. ,QLWLDOL]DWLRQ%ORFN'0$ 7UDQVIHUV During execution of the Am79C976 controller bus mas- ter initialization procedure, the Am79C976 controller will use a burst transfer of seven Dwords to read the ini- tialization block. AD[1:0] is 0 during the address phase indicating a linear burst order. 'HVFULSWRU '0$ 7UDQVIHUV During descriptor read accesses, the byte enable sig- nals will indicate that all byte lanes are active. Should some of the bytes not be needed, then the Am79C976 controller will internally discard the extraneous informa- tion that was gathered during such a read. The settings of SWSTYLE (BCR20, bits 7-0) affect the way the Am79C976 controller performs descriptor read operations. Because of the order in which the descriptor data must be read or written when SWSTYLE is set to 0 or 2, all descriptor read operations are performed in non-burst mode. See Figure 2222. FRAME CLK AD IRDY TRDY C/BE DEVSEL PAR DEVSEL is sampled ADDR BE 0111 PAR 1 234 5 6 78 9 DATA PAR PERR 22929B23 |
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