AM79C976 datasheet(40/309 Pages) AMD

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Am79C976

8/01/00

P R E L I M INARY

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Master Bus Interface Unit

The master Bus Interface Unit (BIU) controls the acqui-

sition of the PCI bus and all accesses to the initializa-

tion block, descriptor rings, and the receive and

transmit buffer memory. Table 3 shows the usage of

PCI commands by the Am79C976 controller in master

mode.

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The Am79C976 logic will determine when a DMA

transfer should be initiated. The first step in any

Am79C976 bus master transfer is to acquire ownership

of the bus. This task is handled by synchronous logic

within the BIU. Bus ownership is requested with the

REQ signal and ownership is granted by the arbiter

through the GNT signal.

Figure 10 shows the Am79C976 controller bus acquisi-

tion. REQ is asserted and the arbiter returns GNT while

an othe r bu s m a s t e r i s tran sfer r i ng dat a. T h e

Am79C976 controller waits until the bus is idle (FRAME

and IRDY deasserted) before it starts driving AD[31:0]

and C/BE[3:0] on clock 5. FRAME is asserted at clock

5 indicating a valid address and command on AD[31:0]

and C/BE[3:0]. REQ is deasserted at the same time

that FRAME is asserted. The Am79C976 controller

does not use address stepping which is reflected by

ADSTEP (bit 7) in the PCI Command register being

hardwired to 0.

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There are four primary types of DMA transfers. The

Am79C976 controller uses non-burst as well as burst

cycles for read and write access to the main memory.

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The Am79C976 controller uses non-burst cycles to ac-

cess descriptors when SWSTYLE (BCR20, bits 7-0) is

0 or 2. All Am79C976 controller non-burst read ac-

cesses are of the PCI command type Memory Read

(type 6). Note that during a non-burst read operation,

all byte lanes will always be active. The Am79C976

controller will internally discard unneeded bytes.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

ADDR

CMD

PAR

2345678

DATA

PAR

PERR

22929B11

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