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80960CF-40 Datasheet(PDF) 70 Page - Intel Corporation |
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80960CF-40 Datasheet(HTML) 70 Page - Intel Corporation |
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70 / 77 page ![]() 64 PRELIMINARY 80960CF-40, -33, -25, -16 A Figure 41. Terminating a Burst with BTERM PCLK ADS A31:4, SUP, DT/R DEN READY W/R DMA, INST, BLAST BTERM A3:2 WAIT D31:0 D/C, BE3:0, LOCK D0 D1 D2 D3 Valid Quad-Word Write Request NWAD = 0, NWDD = 0, NWDA = 0 Ready Enabled 00 01 10 11 Note: READY adds memory access time to data transfers, whether or not the bus access is a burst access. BTERM interrupts a bus access, whether or not the bus access has more data transfers pending. Either the READY signal or the BTERM signal will terminate a bus access if the signal is asserted during the last (or only) data transfer of the bus access. See Note F_CX042A |
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