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UM0434 Datasheet(PDF) 228 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 228 Page - STMicroelectronics |
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228 / 390 page ![]() UM0434 Instruction pipeline and execution timing 229/391 SPE complex integer instruction timing Timings for SPE complex integer instructions are shown in Table 161. The table is sorted by opcode. For the divide instructions, the number of stall cycles is (latency) for following instructions. evstddx 11 evstdh 11 evstdhx 11 evstdw 11 evstdwx 11 evstwhe 11 evstwhex 11 evstwho 11 evstwhox 11 evstwwe 11 evstwwex 11 evstwwo 11 evstwwox 11 Table 161. SPE complex integer instruction timing Instruction Latency Throughput Comments evaddsmiaaw 11 evaddssiaaw 11 evaddumiaaw 11 evaddusiaaw 11 evdivws 12–32 12–32 Timings are data dependent evdivwu 12–32 12–32 Timings are data dependent evmhegsmfaa 11 evmhegsmfan 11 evmhegsmiaa 11 evmhegsmian 11 evmhegumiaa 11 evmhegumian 11 evmhesmf 11 evmhesmfa 11 evmhesmfaaw 11 Table 160. SPE load and store instruction timing (continued) Instruction Latency Throughput Comments |
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