UM0434 datasheet(225/390 Pages) STMICROELECTRONICS

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Instruction pipeline and execution timing

UM0434

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8.7.1

SPE and embedded Floating-Point instruction timing

The tables in this section show instruction timing for SPE and embedded floating-point APU

instructions. Pipelined instructions are shown with cycles of total latency and throughput

cycles. Divide instructions are not pipelined and block other instructions from executing

during divide execution.

Instruction pipelining is affected by the possibility of a floating-point instruction generating an

exception. A load or store class instruction that follows an SPE FPU instruction stalls until it

can be ensured that no previous instruction can generate a floating-point exception. This

determination is based on which floating-point exception enable bits are set (FINVE,

FOVFE, FUNFE, FDBZE, and FINXE) and at what point in the FPU pipeline an exception

can be guaranteed to not occur. Invalid input operands are detected in the first stage of the

pipeline, while underflow, overflow, and inexactness are determined later in the pipeline.

Best overall performance occurs when either floating-point exceptions are disabled, or when

load and store class instructions are scheduled such that previous floating-point instructions

have already resolved the possibility of exceptional results.

SPE integer simple instructions timing

Instruction timing for SPE integer simple instructions is shown in

Table 159. The table is

sorted by opcode. These instructions are issued as a pair of operations.

stwu, e_stwu

None

Aligned

stwux

None

Aligned

stwx

None

Aligned

subfc[o][.]1

None

subfe[o][.]1

None

subfic, e_subfic[.], se_subi[.]1

None

subfme[o][.]1

None

subfze[o][.]1

None

subf[o][.], se_subf, se_sub

1None

3None

twi

3None

wrtee

Completion

wrteei

Completion

xori, e_xori[.]1

None

xoris

1None

xor[.]1

None

Table 158.

Instruction timing by mnemonic (continued)

Mnemonic

Latency Serialization

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