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UM0434 Datasheet(PDF) 222 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 222 Page - STMicroelectronics |
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222 / 390 page  UM0434 Instruction pipeline and execution timing 223/391 crxor, e_crxor 1None divwu[o][.] 6–16 None divw[o][.] 6–16 None With early-out capability timing is data dependent eqv[.]1 None extsb[.], se_extsb 1None extsh[.], se_extsh 1None e_li, e_lis, se_li 1None The UISA defines li as a simplified, mnemonic for addi. e_rlw, e_rlwi 1None isel 1None isync, se_isync 3 Refetch Plus additional synchronization time lbz, e_lbz, se_lbz 1 None Aligned lbzu, e_lbzu 1 None Aligned lbzux, e_lha 1 None Aligned lbzx, e_lhau 1 None Aligned lha, e_lhz 1 None Aligned lhau, e_lhzu 1 None Aligned lhaux 1 None Aligned lhax 1 None Aligned lhbrx 1 None Aligned lhz, se_lhz 1 None Aligned lhzu 1 None Aligned lhzux 1 None Aligned lhzx 1 None Aligned lmw, e_lmw 1 +(n/2) None lwarx 1None lwbrx 1 None Aligned lwz, e_lwz, se_lwz 1 None Aligned lwzu, e_lwzu 1 None Aligned Table 158. Instruction timing by mnemonic (continued) Mnemonic Latency Serialization Comments |
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