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UM0434 Datasheet(PDF) 218 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 218 Page - STMicroelectronics |
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218 / 390 page  UM0434 Instruction pipeline and execution timing 219/391 Figure 29 below, shows timing for interrupt recognition and exception processing overhead. This example shows best-case response timing when an interrupt is received and processed during execution of a load or store instruction. The fetch for the handler is delayed until completion of the load or store, regardless of the number of wait-states. Figure 29. Interrupt recog. & handler instruction exe-load/store in progress Time Slot DEC/EA wait wait Mem Load/Store Instructions IFETCH Abort -- DEC -- p_extint_b Final Sample Point p_iack IFETCH EXE WB DEC First Instruction of handler 123456789 10 IFETCH Stall Stall DEC/ Stall ec_excp_detected* oldpc_->srr0* oldmsr_->srr1* update_esr* update_msr* * Internal Operations 11 WB Abort |
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