UM0434 datasheet(214/390 Pages) STMICROELECTRONICS

214 / 390 page

UM0434

Instruction pipeline and execution timing

215/391

Figure 23.

Pipelined Load/Store instructions

For memory access instructions, wait states may occur. This causes a following memory

access instruction to stall since the following memory access may not be initiated as shown

Figure 24. Here, the first ld/st instruction incurs a wait state on the bus interface, causing

succeeding instructions to stall.

Figure 24.

Pipelined Load/Store instructions with Wait-State

8.3.8

Move to/from SPR instruction pipeline operation

Most mtspr and mfspr instructions are treated like single-cycle instructions in the pipeline

and do not cause stalls. Exceptions are for the MSR, the debug SPRs, the embedded

floating-point APUs, and MMU SPRs, which do cause stalls.

Figure 25 through Figure 25

show examples of mtspr and mfspr instruction timing.

Figure 25 applies to the debug SPRs and the EFPU’s EFSCR. These instructions do not

begin execution until all previous instructions have finished their execute stage. If a

multicycle instruction precedes an mfspr or mtspr instruction, the mfspr or mtspr

instruction does not begin execution until the preceding multicycle instruction moves into the

writeback stage as shown in

Figure 25. In addition, execution of subsequent instructions

stalls until the mfspr and mtspr instructions complete.

First Load/Store Instruction (No Wait)

Time Slot

Second Load/Store Instruction (No Wait)

Add Instruction

IFETCH

DEC/EA

IFETCH

MEM

DEC/EA

IFETCH

EXECUTE

DEC

MEM

First Load/Store Instruction (With Wait)

Time Slot

Second Load/Store Instruction (No Wait)

Add Instruction

IFETCH

Stall (wait)

DEC/EA

IFETCH

Stall

MEM

DEC / EA

EXECUTE

IFETCH

DEC

Stall

MEM

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