UM0434 datasheet(213/390 Pages) STMICROELECTRONICS

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Instruction pipeline and execution timing

UM0434

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Figure 20.

Basic pipeline flow, branch instructions

Figure 21 shows basic pipeline flow for branch speculation.

Figure 21.

Basic pipeline flow, branch speculation

8.3.6

Basic Multi-Cycle instruction pipeline operation

The divide instructions and the load and store multiple instructions require multiple cycles in

the execute stage.

Figure 22.

Basic pipeline flow, Multi-Cycle instructions

Instructions must complete and write back results in order. A single cycle instruction that

follows a multi-cycle instruction must wait for completion of the multi-cycle instruction prior to

its writeback in order to meet the in-order requirement. Result feed-forward paths are

provided so that execution may continue prior to result writeback.

8.3.7

Additional examples of instruction pipeline operation for load & store

Figure 23 shows an example of pipelining two non–data-dependent load or store

instructions with a following data-dependent single-cycle instruction. While the first load or

store begins accessing memory in the MEM stage, the next load or store can be calculating

a new EA in the DEC/EA stage. The add in this example does not stall despite a data

dependency on its preceding load instruction.

DECODE

EXEC

BR Inst.

Time Slot

Target Instruction

EXEC

. . .

IFETCH

Slot0

IFETCH

DECODE

IFETCH

DECODE

Branch Instruction

Time Slot

Target Instruction

Slot0

DECODE

EXEC

(Speculative Fetch)

BTB hit

TFETCH

Slot0

. . .

EXEC

IFETCH

DECODE

Load/Store Multiple Word/Divide Instruction

Time Slot

EXEC0

EXECn

. . .

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