UM0434 datasheet(210/390 Pages) STMICROELECTRONICS

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UM0434

Instruction pipeline and execution timing

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HID0[BPRED] controls if prediction is made for forward or backward branches (or both).

To resolve branch instructions and improve the accuracy of branch predictions, the e200z3

implements a dynamic branch prediction mechanism using an 8-entry branch target buffer

(BTB), a fully associative address cache of branch target addresses. The BTB is

purposefully small to reduce cost and power. It is expected to accelerate the execution of

loops with some potential change of flow within the loop body.

An entry is allocated in the BTB whenever a branch resolves as taken and the BTB is

enabled. Branches that have not been allocated are always predicted as not taken. BTB

entries are allocated on taken branches using a FIFO replacement algorithm.

Each BTB entry holds a 2-bit branch history counter, whose value is incremented or

decremented on a BTB hit, depending on whether the branch was taken. The counter can

assume four different values: strongly taken, weakly taken, weakly not taken, and strongly

not taken.

A branch is predicted as taken on a hit in the BTB with a counter value of strongly or weakly

taken. In this case, the target address contained in the BTB is used to redirect the

instruction fetch stream to the target of the branch prior to the branch reaching the

instruction decode stage. In the case of a mispredicted branch, the instruction fetch stream

returns to the sequential instruction stream after the branch has been resolved.

When a branch is predicted taken and the branch is later resolved (in the branch decode

stage), the value of the counter is updated. A branch whose counter indicates weakly taken

is resolved as taken, the counter increments so that the prediction becomes strongly taken.

If the branch resolves as not taken, the prediction changes to weakly not-taken. The counter

saturates in the strongly taken states when the prediction is correct.

The e200z3 does not implement the static branch prediction that is defined by the PowerPC

architecture. The BO prediction bit in branch encodings is ignored.

Dynamic branch prediction is enabled by setting BUCSR[BPEN]. Clearing BUCSR[BPEN]

disables dynamic branch prediction, in which case the e200z3 predicts every branch as not

taken. Additional control is available in the HID0[BPRED] field to control whether forward or

backward branches (or both) are candidates for entry into the BTB, and thus for branch

prediction. Once a branch is in the BTB, HID0[BPRED] has no further effect on that entry.

The BTB uses virtual addresses for performing tag comparisons. On allocation of a BTB

entry, the EA of a taken branch, along with the current instruction space (as indicated by

MSR[IS]) is loaded into the entry, and the counter value is set to weakly taken. The current

PID value is not maintained as part of the tag information.

The BTB is automatically flushed when the current PID value is updated by an mtspr PID

instruction. Software is otherwise responsible for maintaining coherency in the BTB when a

change in effective-to-real (virtual-to-physical) address mapping is changed. This is

supported by the BUCSR[BBFI] control bit.

UM0434 Datasheet(PDF) 210 Page - STMicroelectronics