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UM0434 Datasheet(PDF) 209 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 209 Page - STMicroelectronics |
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209 / 390 page ![]() Instruction pipeline and execution timing UM0434 210/391 instruction, the data is fed directly into the ALU for execution. No pipeline bubble is incurred in this case. Multiply instructions require one clock to execute. All condition-setting instructions complete in the execute stage of the pipeline. Feed-forwarding allows the result of one instruction to be made available as the source operand(s) of a subsequent instruction so that data-dependent instructions can execute without waiting for previous instructions to write back their results. 8.3.2 Instruction buffers The e200z3 contains a set of instruction buffers that supply instructions into the instruction register (IR) for decoding. Instruction prefetches request a 64-bit double word and the buffer is filled with a pair of instructions at a time, except for the case of a change of flow fetch where the target is to the second (odd) word. In that case, only a 32-bit prefetch is performed to load the instruction buffer. This 32-bit fetch may be immediately followed by a 64-bit prefetch to fill slots 0 and 1 in the event that the branch is resolved to be taken. In normal sequential execution, instructions are loaded into the IR from slot 0, and as a pair of slots are emptied, they are refilled. Whenever a pair of slots is empty, a 64-bit prefetch is initiated that fills the earliest empty slot pairs beginning with slot 0. If the instruction buffer empties, instruction issue stalls, and the buffer is refilled. The first returned instruction is forwarded directly to the IR. Figure 14. Instruction buffers Slot0 Decode MUX IR DATA 0:63 Slot1 Slot2 Slot3 |
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