UM0434 datasheet(211/390 Pages) STMICROELECTRONICS

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Instruction pipeline and execution timing

UM0434

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Figure 15.

Branch target buffer

8.3.3

Single-Cycle instruction pipeline operation

Sequences of single-cycle execution instructions follow the flow in

Figure 16. Instructions

are issued and completed in program order. Most arithmetic and logical instructions fall into

this category.

Figure 16.

Basic pipeline flow, Single-Cycle instructions

8.3.4

Basic load and store instruction pipeline operation

The EA calculations for load and store instructions are performed in the decode stage. The

memory access occurs in the execution stage.

If a load instruction is followed by a dependent ALU instruction, the load data is driven from

the memory in the MEM stage and feed-forwarded into the dependent ALU instruction in the

following cycle. As a result, there is no load-to-use pipeline bubble.

Figure 17 shows the

instruction flow for a load instruction followed by a dependent add instruction.

Figure 17.

A load followed by a dependent add instruction

Tag

Data

Counter

IS = Instruction Space

...

Branch addr[0:29]

Target address[0:29]

Entry

IFETCH

DECODE

EXECUTE

First Inst.

Time Slot

FFwd/WB

Second Instruction

Third Instruction

IFETCH

DECODE

EXECUTE

FFwd/WB

IFETCH

DECODE

EXECUTE

FFwd/WB

DEC/EA

MEM

First Load Instruction

Time Slot

MEM

Second Add Instruction

DECODE

EXECUTE

MEM

IFETCH

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