UM0434 datasheet(207/390 Pages) STMICROELECTRONICS

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Instruction pipeline and execution timing

UM0434

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8.1.3

Branch unit

The branch unit contains an eight-entry branch target buffer (BTB) to accelerate execution

of branch instructions.

Untaken conditional branches execute in a single clock. Branches with successful target

prefetching have an effective execution time of one clock cycle. All other taken branches

have an execution time of two clocks.

8.1.4

Instruction decode unit

The decode unit includes the instruction buffers. A single instruction can be decoded each

cycle. The major functions of the decode logic are as follows:

●

Opcode decoding to determine the instruction class and resource requirements for

each instruction being decoded.

●

Source and destination register dependency checking.

●

Execution unit assignment.

●

Determine any decode serializations and inhibit subsequent instruction decoding.

The decode unit operates in a single processor clock cycle.

8.1.5

Exception handling

The exception handling unit includes logic to handle exceptions, interrupts, and traps.

8.2

Execution units

The core data execution units consist of the integer unit and the load/store unit. Included in

the execution units section are the general purpose registers (GPRs). Instructions with data

dependencies begin execution when all such dependencies are resolved.

8.2.1

Integer execution unit

The integer execution unit is used to process arithmetic and logical instructions. Adds,

subtracts, compares, count leading zeros, shifts, and rotates execute in a single cycle.

Multiply instructions have a latency and throughput rate of 1 cycle.

Divide instructions have a variable latency (6–16 cycles) depending on the operand data.

The worst case integer divide requires 16 cycles. While the divide is running, the rest of the

pipeline is unavailable for additional instructions (blocking divide).

8.2.2

Load/Store unit

The load/store unit executes instructions that move data between the GPRs and the

memory subsystem. A load followed by a dependent instruction does not incur any pipeline

stall, except when the dependent instruction is a load/store instruction, and the latter

instruction is using the previous load data for its effective address (EA) calculation.

Loads, when free of the above EA calculation dependency, execute with a maximum

throughput of one per cycle and one-cycle latency. Store data can be fed forward from an

immediately preceding load with no stall.

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