UM0434 datasheet(203/390 Pages) STMICROELECTRONICS

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Memory management unit

UM0434

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7.6.1

MMU configuration register (MMUCFG)

MMUCFG provides configuration information for the MMU supplied with this version of the

e200z3 CPU core. See

Chapter 4.16.2: MMU configuration register (MMUCFG).”

7.6.2

TLB0 and TLB1 configuration registers

TLB0CFG and TLB1CFG provide configuration information for the MMU TLBs supplied with

this version of the e200z3 CPU core. See

Chapter 4.16.3: TLB configuration registers

(TLBnCFG).”

7.6.3

Data exception address register (DEAR)

DEAR, described in

Chapter : Data exception address register (DEAR),” is loaded with the

effective address of the data access that results in an alignment, data TLB miss, or data

storage interrupt.

7.6.4

MMU control and status register 0 (MMUCSR0)

MMUCSR0, shown in

Chapter 4.16.1,”controls the state of the MMU.

7.6.5

MMU assist registers (MAS)

The e200z3 uses MAS0–MAS4 and MAS6 SPRs to facilitate reading, writing, and searching

the TLBs. The e200z3 does not implement MAS5, because the tlbsx instruction only

searches based on a single SPID value.

MAS registers are described in

Chapter 4.16.4.”

MAS registers summary

The fields of the MAS registers are summarized in

Table 155.

MMU assist registers summary

34 35

59 60 61 62 63

MAS

—

TLBSE

—ESEL

—

MAS

VALI

IPRO

—TID

—

TSIZ

—

MAS

EPN

—

VLE W

M G

MAS

RPN

—

UX SX

MAS

—

TBSEL

—

TIDSELD

—

TSIZED

—

VLE

MAS

—

SPID

—

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