UM0434 datasheet(201/390 Pages) STMICROELECTRONICS

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Memory management unit

UM0434

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7.5.1

Translation reload

The TLB reload function is performed in software with some hardware assistance. This

hardware assistance consists of the following:

●

Five 32-bit MMU assist registers (MAS0–MAS4, MAS6) for support of the tlbre, tlbwe,

and tlbsx TLB management instructions.

●

Loading of MAS0–MAS2 based upon defaults in MAS4 for TLB miss exceptions. This

automatically generates most of the TLB entry.

●

Loading of the data exception address register (DEAR) with the EA of the load, store,

or cache management instruction that caused an alignment, data TLB miss, or data

storage interrupt.

●

The tlbwe instruction. When tlbwe is executed, the new TLB entry contained in MAS0–

MAS2 is written into the TLB.

7.5.2

Reading the TLB

The TLB array can be read by first writing the necessary information into MAS0 using mtspr

and then executing the tlbre instruction. To read an entry from TLB1, MAS0[TLBSEL] must

be set to 01 and MAS0[ESEL] must be set to point to the desired entry. After tlbre executes,

MAS1–MAS3 are updated with the data from the selected TLB entry. See

Chapter 7.4:

Software interface and TLB instructions on page 200.”

7.5.3

Writing the TLB

The TLB1 array can be written by first writing the necessary information into MAS0–MAS3

using mtspr and then executing the tlbwe instruction. To write an entry into TLB1, the

TLBSEL field in MAS0 must be set to 01, and the ESEL bits in MAS0 must be set to point to

the desired entry. When the tlbwe instruction is executed, the TLB entry information stored

in MAS1–MAS3 is written into the selected TLB entry. See

Chapter 7.4: Software interface

and TLB instructions on page 200.”

7.5.4

Searching the TLB

TLB1 can be searched using a tlbsx by first writing the necessary information into MAS6.

The tlbsx instruction searches using EPN[0–19] from the GPR selected by the instruction,

SAS (search AS bit) in MAS6, and SPID in MAS6. If the search is successful, the given TLB

entry information is loaded into MAS0–MAS3. The valid bit in MAS1 is used as the success

flag. If the search is successful, the valid bit in MAS1 is set; if unsuccessful, it is cleared. The

tlbsx instruction is useful for finding the TLB entry that caused a data or instruction storage

interrupt. See

Chapter 7.4: Software interface and TLB instructions on page 200.”

7.5.5

TLB coherency control

The e200z3 core provides the ability to invalidate a TLB entry as described in the Book E

PowerPC architecture. The tlbivax instruction invalidates local TLB entries only. No

broadcast is performed, as no hardware-based coherency support is provided.

The tlbivax instruction invalidates by effective address only. This means that only the TLB

entry’s EPN bits are used to determine if the TLB entry should be invalidated. Therefore, a

single tlbivax can invalidate multiple TLB entries, because the AS and TID fields of the

entries are ignored.

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