UM0434 datasheet(198/390 Pages) STMICROELECTRONICS

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UM0434

Memory management unit

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7.3.2

Replacement algorithm for TLB1

The replacement algorithm for TLB1 must be implemented completely by system software.

Thus, when an entry in TLB1 is to be replaced, the software can select which entry to

replace and write the entry number to the MAS0[ESEL] field before executing a tlbwe

instruction.

Alternately, the software can load the entry number of the next desired victim into

MAS0[NV]. The e200z3 then automatically loads MAS0[ESEL] from MAS0[NV] on a TLB

error condition as shown in

Figure 11.

See

Table 156 for a complete description of MAS register updates on various exception

conditions.

Figure 11.

Victim selection

7.3.3

The G bit (of WIMGE)

The G bit provides protection from bus accesses that could be canceled due to an exception

on a prior uncompleted instruction.

If G = 1 (guarded), these types of accesses must stall until the exception status of any

instructions in progress is known. If G = 0 (unguarded), these accesses may be issued to

the bus regardless of the completion status of other instructions. Because the core does not

make requests for load or store instructions until it is known that prior instructions will

complete without exceptions, the G bit is essentially ignored. Proper operation always

occurs to guarded storage.

7.3.4

TLB entry field summary

Table 152 summarizes the fields of e200z3 TLB entries.

Note:

All of these fields are defined at the Freescale Book E level.

MAS0

ESEL

On tlbwe SelectsEntry

TLB Miss (TLB Error Interrupt)

Written by Software

Table 152.

TLB entry bit fields for e200z3

Field

Description

Valid bit for entry

Translation address space (compared with AS bit of the current access)

TID[0–7]

Translation ID (compared with PID0 or TIDZ (all zeros))

EPN[0–19]

Effective page number (compared with effective address)

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