UM0434 datasheet(196/390 Pages) STMICROELECTRONICS

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UM0434

Memory management unit

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7.2.5

Permissions

An operating system may restrict access to virtual pages by selectively granting permissions

for user-mode read, write, and execute, and supervisor-mode read, write, and execute on a

per-page basis. These permissions can be set up for a particular system (for example,

program code may be execute only, and data structures may be mapped as read/write/no-

execute) and be changed by the operating system based on application requests and

operating system policies.

The UX, SX, UW, SW, UR, and SR access control bits are provided to support selective

permissions (access control):

●

SR—Supervisor read permission. Allows loads and load-type cache management

instructions to access the page while in supervisor mode (MSR[PR = 0]).

●

SW—Supervisor write permission. Allows stores and store-type cache management

instructions to access the page while in supervisor mode (MSR[PR = 0]).

●

SX—Supervisor execute permission. Allows instruction fetches to access the page and

instructions to be executed from the page while in supervisor mode (MSR[PR = 0]).

●

UR—User read permission. Allows loads and load-type cache management

instructions to access the page while in user mode (MSR[PR = 1]).

●

UW—User write permission. Allows stores and store-type cache management

instructions to access the page while in user mode (MSR[PR = 1]).

●

UX—User execute permission. Allows instruction fetches to access the page and

instructions to be executed from the page while in user mode (MSR[PR = 1]).

If the translation match was successful, the permission bits are checked as shown in

Figure 9. If the access is not allowed by the access permission mechanism, the processor

generates an instruction or data storage interrupt (ISI or DSI).

Figure 9.

Granting of access permission

7.3

Translation lookaside buffer

The EIS architecture defines support for zero or more TLBs in an implementation, each with

its own characteristics, and provides configuration information for software to query the

existence and structure of TLBs through a set of SPRs—MMUCFG, TLB0CFG, TLB1CFG,

and so on. By convention, TLB0 is used for a set-associative TLB with fixed page sizes,

Access Granted

Instruction Fetch

MSR[PR]

TLB_entry[UX]

TLB_entry[SX]

TLB_entry[UR]

TLB_entry[SR]

TLB_entry[UW]

TLB_entry[SW]

Load-Class Data Access

Store-Class Data Access

TLB Match (see Figure 5-2)

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