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UM0434 Datasheet(PDF) 200 Page - STMicroelectronics

Part # UM0434
Description  The primary objective of this user?셲 manual is to describe
PDF  390 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UM0434 Datasheet(HTML) 200 Page - STMicroelectronics

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UM0434
Memory management unit
201/391
the search occurs if a TLB invalidate or replacement removes the entry between the time
the exception is recognized and when the tlbsx is executed.
The supervisor instructions tlbre, tlbwe, tlbsx, tlbivax, and tlbsync are fully described in
the
EREF.
●
TLB Read Entry (tlbre)—Causes contents of the TLB entry specified by
MAS0[TLBSEL,ESEL]) to be placed into MAS1–MAS3.
Table 156 describes how MAS
fields are updated.
●
TLB Write Entry (tlbwe)—Causes the contents of certain fields within the MAS1,
MAS2, and MAS3 to be written into the TLB entry specified by MAS0[TLBSEL,ESEL].
Table 156 describes how MAS fields are updated.
●
TLB Search Indexed (tlbsx)—Updates the MAS registers conditionally based on
success or failure of a TLB lookup. The lookup is controlled by an effective address
provided by rB as specified in the instruction encoding, and by MAS6[SAS,SPID]. The
values placed into MAS0–MAS3 differ depending on the success of the search.
Table 156 describes how MAS fields are updated.
●
TLB Invalidate (tlbivax)—Invalidates TLB entries that correspond to the virtual address
calculated by this instruction. The address is detailed in
Table 153. No other
information except for that shown in
Table 153 is used for the invalidation (AS and TID
values are ignored).
Additional information about the targeted TLB entries is encoded in two of the lower bits
of the effective address calculated by the tlbivax.
EA[0–19] are used to perform the tlbivax invalidation of TLB1.
t
●
TLB Synchronize (tlbsync)—Treated as a privileged no-op by the e200z3.
7.5
TLB operations
This section describes how the software (with some hardware assistance) maintains TLB1.
Table 153.
tlbivax EA bit definitions
Bits
Field
0–19
EA[0–19]
20–27 Reserved(1)
1.
These bits should be zero for future compatibility. They are ignored.
28
TLBSEL (1 = TLB1). Should be set, for future compatibility and to ensure that TLB1 is
targeted by the invalidate.
29
INV_ALL. If set, indicates that the invalidate operation needs to completely invalidate all
TLB1 entries that are not marked as invalidation protected (IPROT = 1)
30–31 Reserved 1



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