UM0434 datasheet(202/390 Pages) STMICROELECTRONICS

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UM0434

Memory management unit

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7.5.6

TLB miss exception update

When a TLB miss exception occurs, MAS0–MAS3 are updated with the defaults specified in

MAS4 and the AS and EPN[0–19] of the access that caused the exception. In addition, the

ESEL bits are updated with the replacement entry value. This sets up all the TLB entry data

necessary for a TLB write except for the RPN[0–19], the U0–U3 user bits, and the

UX/SX/UW/SW/UR/SR permission bits, all of which are stored in MAS3. Thus, if the defaults

stored in MAS4 are applicable to the TLB entry to be loaded, the TLB miss exception

handler only has to update MAS3 through mtspr before executing tlbwe. If the defaults are

not applicable to the TLB entry being loaded, the TLB miss handler must update MAS0–

MAS2 before performing the TLB write.

See

Table 156 for more details on the automatic updates to the MAS registers on

exceptions.

7.5.7

TLB load on reset

During reset, all TLB entries except entry 0 are automatically invalidated by the hardware.

TLB entry 0 is also loaded with the default values in

Table 154.

7.6

MMU configuration and control registers

Information about the configuration for a given MMU implementation is available to system

software by reading the contents of the MMU configuration SPRs. These SPRs describe the

architectural version of the MMU, the number of TLB arrays, and the characteristics of each

TLB array. Additionally, there are a number of MMU control and assist registers summarized

Chapter 4.16.4: MMU assist registers (MAS0–MAS4, MAS6) on page 91.”

Table 154.

TLB entry 0 values after Reset

Field

Reset Value

Comments

VALID

Entry is valid.

Address space 0

TID[0–7]

0x00

TID value for shared (global) page

EPN[0–19]

p_rstbase[0:19]

value

Page address present on

p_rstbase[0:19]. See Chapter 9: External

core complex interfaces.”

RPN[0–19]

p_rstbase[0:19]

value

Page address present on

p_rstbase[0:19]. See Chapter 9: External

core complex interfaces.”

SIZE[0–3]

0001

4KB page size

SX/SW/SR

111

Full supervisor mode access allowed

UX/UW/UR

111

Full user mode access allowed

WIMG

0100

Cache-inhibited, non-coherent

p_rst_endmode

value

Value present on

p_rst_endmode. See Chapter 9: External core

complex interfaces.”

U0–U3

0000

User bits

IPROT

Page is protected from invalidation.

VLE

p_rst_vlemode

value

Value present on

p_rst_vlemode signal. See Table 167 for more

information.

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