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UM0434 Datasheet(PDF) 206 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 206 Page - STMicroelectronics |
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206 / 390 page ![]() UM0434 Instruction pipeline and execution timing 207/391 Figure 12. e200z3 block diagram 8.1.1 Control unit The control unit coordinates the instruction fetch unit, branch unit, instruction decode unit, instruction issue unit, completion unit, and exception handling logic. 8.1.2 Instruction unit The instruction unit controls the flow of instructions to the instruction buffers and decode unit. Six prefetch buffers allow the instruction unit to fetch instructions ahead of actual execution, and serve to decouple memory and the execution pipeline. CPU Load/ Data Memory Address Store Unit Instruction Unit Branch Unit PC Unit Instruction Buffer GPR CR SPR Multiply Unit Data Bus Interface Unit Control 32 64 N OnCE/Nexus Interface Control Data (mtspr/mfspr) Integer Execution Unit External SPR CTR XER LR Data Address Control 32 64 N Control Logic Control Logic Management Unit |
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