UM0434 datasheet(197/390 Pages) STMICROELECTRONICS

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Memory management unit

UM0434

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TLB1 is used for a fully-associative TLB with variable page sizes, and TLB2 is arbitrarily

defined by an implementation. The e200z3 MMU supports a single TLB that is fully

associative and supports variable page sizes; thus it corresponds to TLB1 in the

programming model. For the rest of this document, TLB, TLBCAM, and TLB1 are used

interchangeably.

The TLB on the e200z3 MMU (TLB1) consists of a 16-entry, fully-associative content-

addressable memory (CAM) array with support for nine page sizes. To perform a lookup, the

TLB is searched in parallel for a matching TLB entry. The contents of a matching TLB entry

are then concatenated with the page offset of the original effective address. The result

constitutes the real (physical) address of the access.

A hit to multiple TLB entries is considered to be a programming error. If this occurs, the TLB

generates an invalid address and TLB entries may be corrupted (an exception will not be

reported).

The structure of TLB1 is shown in

Figure 10.

e200z3 TLB1 organization

7.3.1

IPROT invalidation protection in TLB1

The IPROT bit in TLB1 is used to protect TLB entries from invalidation. TLB1 entries with

IPROT set are not invalidated by a tlbivax instruction executed by this processor (even

when the INV_ALL command is indicated), or by a flash invalidate initiated by writing to

MMUCSR0[TLB1_FI]. The IPROT bit can be used to protect critical code and data such as

interrupt vectors/handlers in order to guarantee that the instruction fetch of those vectors

never takes a TLB miss exception. Entries with IPROT set can only be invalidated by writing

a 0 to the valid bit of the entry (by using the MAS registers and executing the tlbwe

instruction).

Invalidation operations generated by execution of the tlbivax instruction are guaranteed to

invalidate the entry that translates the address specified in the operand of the tlbivax

instruction. Additional entries may also be invalidated by this operation if they are not

protected with IPROT. A precise invalidation can be performed by writing a 0 to the valid bit

of a TLB entry.

TLB1

Compare

RPN

Hit

Real Address

(translated bits, depending on page size)

Virtual Address

UM0434 Datasheet(PDF) 197 Page - STMicroelectronics