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UM0434 Datasheet(PDF) 193 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 193 Page - STMicroelectronics |
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193 / 390 page  Memory management unit UM0434 194/391 Figure 7. Effective to real address translation flow 32-Bit Effective Address 32-Bit Real Address Virtual Address NOTE: n = 32–log2 (page size) n> = 20 n = 20 for 4-Kbyte page size PID Effective Page Address Offset 0n 31 TLB Multiple-Entry MSR[IS] for Instruction Fetch AS MSR[DS] for Data Access RPN field of matching entry n–1 Real Page Number Offset 0n 31 n–1 Effective Page Number Byte Address Real Page Number Byte Address 32-bit Effective Address (EA) 32-Bit Real Address 15–20 Bits* >12 Bits* 15–20 Bits* >12 Bits* MMU (Unified) Three 41-Bit Virtual Addresses (VAs) 8 Bits MSR ··· IS DS ··· Instruction Access Data Access AS PID0 * Number of bits depends on page size (4 Kbytes–128 Mbytes) 32-Entry Fully–Assoc. VSP Array (TLB1) MAS Registers |
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