UM0434 datasheet(189/390 Pages) STMICROELECTRONICS

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Interrupts and exceptions

UM0434

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Instruction fetch and execution resume, using the new MSR value, at a location specific to

the exception type. The location is determined by the IVPR and an IVOR specific for each

type of interrupt (see

Table 114). A new operating context is selected using the low-order

three bits of the specific IVOR selected by the type of interrupt.

Table 149 shows the MSR settings for different interrupt categories. Note that reserved and

preserved MSR bits are unimplemented and are read as 0.

6.8.1

Enabling and disabling exceptions

When a condition exists that may cause an exception to be generated, it must be

determined whether the exception is enabled for that condition.

●

System reset exceptions cannot be masked.

●

A machine check exception can occur only if the machine check enable, MSR[ME], = 1.

If ME = 0, the processor goes directly into checkstop state when a machine check

exception condition occurs. Individual machine check exceptions can be enabled and

disabled through HID0 bits.

●

Asynchronous, maskable non-critical exceptions (such as the external input and

decrementer) are enabled by setting MSR[EE]. When EE = 0, recognition of these

exception conditions is delayed. EE is cleared automatically when a non-critical or

critical interrupt is taken to mask further recognition of conditions causing those

exceptions.

●

Asynchronous, maskable critical exceptions (such as critical input and watchdog timer)

are enabled by setting MSR[CE]. When CE = 0, recognition of these exception

conditions is delayed. CE is cleared automatically when a critical interrupt is taken to

mask further recognition of conditions causing those exceptions.

●

Synchronous and asynchronous debug exceptions are enabled by setting MSR[DE]. If

DE = 0, recognition of these exception conditions is masked. DE is cleared

Table 149.

MSR setting due to interrupt

Bits MSR definition Reset setting Non-critical interrupt Critical interrupt Debug interrupt

UCLE

SPE

—

—/0(1)

Conditionally cleared based on control bits in HID0

—/01

—

FE0

—

—/01

FE1

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