UM0434 datasheet(187/390 Pages) STMICROELECTRONICS

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Interrupts and exceptions

UM0434

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Debug: BRT

Debug: Trap

Debug: RET

Debug: CRET

Attempted execution of a taken branch instruction

Condition specified in tw or twi instruction met.

Attempted execution of a rfi instruction

Attempted execution of an rfci instruction

Exceptions require corresponding debug event enabled,

MSR[DE]=1, and DBCR0[IDM]=1.

Program: trap

Condition specified in tw or twi instruction met and not a

debug trap exception

System call

Execution of the system call (sc, se_sc) instruction.

SPE floating-point

data

NaN, infinity, or denormalized data detected as input or

output, or underflow, overflow, divide by zero, or invalid

operation in the SPE APU.

SPE round

Inexact result

Alignment

lmw, stmw, lwarx, or stwcx. Not word aligned. dcbz with

cache disabled or not present

Debug with

concurrent DTLB or

data storage

interrupt:

DAC/IAC linked(2)

DAC unlinked2

Debug with concurrent DTLB or data storage interrupt.

DBSR[IDE] also set.

Data address compare linked with instruction address

compare

Data address compare unlinked

Note: Exceptions require corresponding debug event

enabled, MSR[DE]=1, and DBCR0[IDM]=1. In this case, the

debug exception is considered imprecise and DBSR[IDE] is

set. Saved PC points to the load or store instruction causing

the DAC event.

Data TLB error

Data translation lookup miss in the TLB.

Data storage

Access control.

Byte ordering due to misaligned access across page

boundary to pages with mismatched E bits.

Precise external termination error (

p_tea_b assertion and

precise recognition) and MSR[EE]=1

Debug: IRPT

Debug: CIRPT

Interrupt taken (non-critical)

Critical interrupt taken (critical only)

Note: Exceptions require corresponding debug event

enabled, MSR[DE]=1 and DBCR0[IDM]=1.

Table 148.

e200z3 exception priorities (continued)

Priority

Exception

Cause

IVOR

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