UM0434 datasheet(191/390 Pages) STMICROELECTRONICS

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Memory management unit

UM0434

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Memory management unit

This chapter describes the implementation details of the e200z3 core complex MMU relative

to the Book E architecture and the Freescale Book E standards.

7.1

Overview

The e200z3 memory management unit is a 32-bit PowerPC Book E–compliant

implementation.

7.1.1

MMU features

The MMU of the e200z3 core has the following feature set:

●

Freescale Book E implementation standard (EIS) MMU architecture compliant

●

32-bit effective address translated to 32-bit real address (using a 41-bit interim virtual

address)

●

16-entry, fully associative, translation lookaside buffer (TLB1) that supports the nine

page sizes (4 Kbytes, 16 Kbytes, 64 Kbytes, 256 Kbytes, 1 Mbyte, 4 Mbytes,

16 Mbytes, 64 Mbytes, 256 Mbytes), shown in

Table 151

●

One 32-bit PID register (PID0) for supporting up to 255 translation IDs at any time in

the TLB

●

No page table format defined; software is free to use its own page table format

●

Hardware assist for TLB miss exceptions

●

TLB1 managed by tlbre, tlbwe, tlbsx, tlbsync, and tlbivax instructions and six MMU

assist (MAS) registers

●

IPROT bit implemented in TLB1 prevents invalidations, protecting critical entries (so

designated by having the IPROT bit set) from being invalidated.

7.1.2

TLB entry maintenance features summary

The TLB entries of the e200z3 core complex must be loaded and maintained by the system

software; this includes performing any required table search operations in memory. The

e200z3 provides support for maintaining TLB entries in software with the resources shown

Table 150. Note that many of these features are defined at the Freescale Book E level.

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