UM0434 datasheet(194/390 Pages) STMICROELECTRONICS

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UM0434

Memory management unit

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7.2.1

Effective addresses

Instruction accesses are generated by sequential instruction fetches or due to a change in

program flow (branches and interrupts). Data accesses are generated by load, store, and

cache management instructions. The e200z3 instruction fetch, branch, and load/store units

generate 32-bit effective addresses. The MMU translates these effective addresses to 32-bit

physical (real) addresses that are then used for memory accesses.

The PowerPC Book E architecture divides the effective (virtual) and real (physical) address

space into pages. The page represents the granularity of effective address translation,

permission control, and memory/cache attributes. The e200z3 MMU supports nine page

sizes (4 Kbytes to 256 Mbytes, as defined in

Table 151). In order for an effective-to-real

address translation to exist, a valid entry for the page containing the effective address must

be in a TLB. Accesses to addresses for which no TLB entry exists (a TLB miss) cause

instruction or data TLB errors.

7.2.2

Address spaces

The PowerPC Book E architecture defines two effective address spaces for instruction

accesses and two effective address spaces for data accesses. The current effective address

space for instruction or data accesses is determined by the value of MSR[IS] (instruction

address space bit) and MSR[DS] (data address space bit), respectively. The address space

indicator (the corresponding value of either MSR[IS] or MSR[DS]) is used in addition to the

effective address generated by the processor for translation into a physical address by the

TLB mechanism. Because MSR[IS] and MSR[DS] are both cleared when an interrupt

occurs, an address space value of 0 can be used to denote interrupt-related address spaces

(or possibly all system software address spaces). An address space value of 1 can be used

to denote non–interrupt-related address spaces or possibly all user address spaces.

The address space associated with an instruction or data access is included as part of the

virtual address in the translation process (AS).

7.2.3

Virtual addresses and process ID

The PowerPC Book E architecture requires a process ID (PID) value to be associated with

each effective address (instruction or data) generated by the processor to construct a virtual

address for each access. At the Book E level, a single PID register is defined as a 32-bit

included as part of the virtual address in the translation process (PID0).

For the e200z3 MMU, the PID is 8 bits in length. The most significant 24 bits are

unimplemented and read as 0. The

p_pid0[0:7] interface signals indicate the current

process ID.

The core complex implements a single process ID (PID) register, PID0, as an SPR shown in

Chapter 4.16.5 on page 96.” The current value in the PID register is used in the TLB look-up

process and compared with the TID field in all the TLB entries. If the PID value in PID0

matches with a TLB entry in which all the other match criteria are met, that entry is used for

translation.

Note that when a TID value in a TLB entry is all zeros, it always causes a match in the PID

compare (effectively ignoring the values of the PID register). Thus, the operating system can

set the values of all the TIDs to zero, effectively eliminating the PID value from all translation

comparisons.

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