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UM0434

Interrupts and exceptions

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6.6.20

SPE Floating-Point round interrupt (IVOR34)

The SPE floating-point round interrupt is taken when an SPE floating-point instruction

generates an inexact result and inexact exceptions are enabled.

Table 147 lists register settings when an SPE floating-point round interrupt is taken.

6.7

Exception recognition and priorities

The following list of exception categories describes how the e200z3 handles exceptions up

to the point of signaling the appropriate interrupt to occur. Also, instruction completion is

defined as updating all architectural registers associated with that instruction as necessary,

and then removing the instruction from the pipeline.

●

Interrupts caused by asynchronous events (exceptions). These exceptions are further

distinguished by whether they are maskable and recoverable.

–

Asynchronous, non-maskable, non-recoverable: System reset by assertion of

p_reset_b.

Has highest priority and is taken immediately regardless of other pending

exceptions or recoverability. (Includes watchdog timer reset control and debug

reset control)

–

Asynchronous, maskable, non-recoverable: Machine check interrupt.

Has priority over any other pending exception except system reset conditions; is

dependent on the source of the exception. Typically non-recoverable.

–

Asynchronous, maskable, recoverable: External input, fixed-interval timer,

decrementer, critical input, unconditional debug, external debug event, debug

counter event, and watchdog timer interrupts.

Before handling this type of exception, the processor needs to reach a recoverable

state. A maskable recoverable exception remains pending until taken or cancelled

by software.

Table 147.

SPE Floating-Point round interrupt register settings

Setting description

SRR0

Set to the effective address of the instruction following the excepting SPE instruction.

SRR1

Set to the contents of the MSR at the time of the interrupt

MSR

UCLE

SPE

—

FE0

—

FE1

ESR

SPE, [VLEMI]. All other bits cleared.

MCSR

Unchanged

DEAR

Unchanged

Vector

IVPR[32–47] || IVOR34[48–59] || 0b0000

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