UM0434 datasheet(181/390 Pages) STMICROELECTRONICS

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Interrupts and exceptions

UM0434

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6.6.17

System reset

The core implements the system reset, which is not an interrupt defined in Book E. The

system reset exception is a non-maskable, asynchronous exception signaled to the

processor through the assertion of system-defined signals.

A system reset may be initiated as follows:

●

By asserting the

p_reset_b input. p_reset_b must remain asserted for a period

(specified in the hardware specifications) that allows internal logic to be reset.

Assertion for less than the required interval causes unpredictable results.

●

By asserting

m_por during power-on reset. m_por must be asserted during power up

and must remain asserted for a period (specified in the hardware specifications) that

allows internal logic to be reset. Assertion for less than the required interval causes

unpredictable results.

●

By watchdog timer reset control

●

By debug reset control

MSR

UCLE

SPE

—/0(2)

—/02

—

FE0

FE1

DBSR(3)

Unconditional debug event:

Instruction complete debug event:

Branch taken debug event:

Interrupt taken debug event:

Critical interrupt taken debug

event:

Trap instruction debug event:

Instruction address compare:

Data address compare:

Return debug event:

Critical return debug event:

Debug counter event:

External debug event:

(optional)

Imprecise debug event flag

UDE

ICMP

BRT

IRPT

CIRPT

TRAP

{IAC1, IAC2, IAC3, IAC4}

{DAC1R, DAC1W, DAC2R, DAC2W}

RET

CRET

{DCNT1, DCNT2}

{DEVT1, DEVT2}

{IDE}

ESR

Unchanged

MCSR

Unchanged

DEAR

Unchanged

Vector

IVPR[32–47] || IVOR15[48–59] || 0b0000

Assumes that the debug interrupt is precise

Conditional based on HID0 control bits.

Note that multiple DBSR bits may be set.

Table 141.

Debug interrupt register settings (continued)

Setting description

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