UM0434 datasheet(177/390 Pages) STMICROELECTRONICS

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Interrupts and exceptions

UM0434

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6.6.13

Watchdog timer interrupt (IVOR12)

The e200z3 implements the watchdog timer interrupt as defined in Book E. The exception is

triggered by the first enabled watchdog timeout.

A watchdog timer interrupt occurs when no higher priority exception exists, a watchdog

timer exception exists (TSR[WIS]=1), and the interrupt is enabled (both TCR[WIE] and

MSR[CE] = 1).

The TSR holds the watchdog interrupt bit set by the timer facility when an exception is

detected. Software must clear this bit in the interrupt handler to avoid repeated watchdog

interrupts.

Table 137 lists register settings when a watchdog timer interrupt is taken.

MSR[DE] is not automatically cleared by a watchdog timer interrupt, but can be configured

to be cleared through HID0[CICLRDE]. See

Chapter 4.13.1: Hardware implementation

dependent register 0 (HID0) on page 84.”

MSR

UCLE

SPE

—

FE0

—

FE1

ESR

Unchanged

MCSR

Unchanged

DEAR

Unchanged

Vector

IVPR[32–47] || IVOR11[48–59] || 0b0000

Table 136.

Fixed-Interval timer interrupt register settings (continued)

Setting description

Table 137.

Watchdog timer interrupt register settings

Setting description

CSRR0

Set to the effective address of the instruction that the processor would have attempted to

execute next if no exception conditions were present.

CSRR1

Set to the contents of the MSR at the time of the interrupt

MSR

UCLE

SPE

—

FE0

0/—(1)

FE1

DE is cleared when the debug APU is disabled. Clearing of DE is optionally supported by control in HID0

when the debug APU is enabled.

ESR

Unchanged

MCSR

Unchanged

DEAR

Unchanged

Vector

IVPR[32–47] || IVOR12[48–59] || 0b0000

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