UM0434 datasheet(176/390 Pages) STMICROELECTRONICS

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UM0434

Interrupts and exceptions

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6.6.11

Decrementer interrupt (IVOR10)

The e200z3 implements the decrementer exception as described in Book E. A decrementer

interrupt occurs when no higher priority exception exists, a decrementer exception condition

exists (TSR[DIS]=1), and the interrupt is enabled (both TCR[DIE] and MSR[EE]=1).

The timer status register (TSR) holds the decrementer interrupt bit set by the timer facility

when an exception is detected. The interrupt handler must clear this bit to avoid repeated

decrementer interrupts.

Table 135 lists register settings when a decrementer interrupt is taken.

6.6.12

Fixed-Interval timer interrupt (IVOR11)

The e200z3 implements the fixed-interval timer exception as defined in Book E. The

triggering of the exception is caused by selected bits in the time base register changing from

0 to 1.

A fixed-interval timer interrupt occurs when no higher priority exception exists, a fixed-

interval timer exception exists (TSR[FIS]=1), and the interrupt is enabled (both TCR[FIE]

and MSR[EE]=1).

The timer status register (TSR) holds the fixed-interval timer interrupt bit set by the timer

facility when an exception is detected. Software must clear this bit in the interrupt handler to

avoid repeated fixed-interval timer interrupts.

Table 136 lists register settings when a fixed-interval timer interrupt is taken.

Table 135.

Decrementer interrupt register settings

Setting description

SRR0

Set to the effective address of the instruction that the processor would have attempted to

execute next if no exception conditions were present.

SRR1

Set to the contents of the MSR at the time of the interrupt

MSR

UCLE

SPE

—

FE0

—

FE1

ESR

Unchanged

MCSR

Unchanged

DEAR

Unchanged

Vector

IVPR[32–47] || IVOR10[48–59] || 0b0000

Table 136.

Fixed-Interval timer interrupt register settings

Setting description

SRR0

Set to the effective address of the instruction that the processor would have attempted to

execute next if no exception conditions were present.

SRR1

Set to the contents of the MSR at the time of the interrupt.

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