UM0434 datasheet(172/390 Pages) STMICROELECTRONICS

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UM0434

Interrupts and exceptions

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6.6.5

External input interrupt (IVOR4)

An external input exception is signaled to the processor by the assertion of the external

interrupt input (

p_extint_b), a level-sensitive signal expected to remain asserted until the

e200z3 acknowledges the external interrupt. If

p_extint_b is negated early, recognition of

the interrupt request is not guaranteed. When the e200z3 detects the exception, if the

exception is enabled by MSR[EE], the e200z3 takes an external input interrupt.

An external input interrupt may be delayed by other higher priority exceptions or if MSR[EE]

is cleared when the exception occurs.

Table 130 lists register settings when an external input interrupt is taken.

IVOR4 is the vector offset register used by autovectored external input interrupts to

determine the interrupt handler location. The e200z3 also provides the capability to directly

vector external input interrupts to multiple handlers by allowing an external input interrupt

request to be accompanied by a vector offset. The

p_voffset[0:11] input signals are used in

MSR

UCLE

SPE

—

FE0

—

FE1

ESR

[XTE, BO, MIF, VLEMI]. All other bits cleared.

MCSR

Unchanged

DEAR

Unchanged

Vector

IVPR[32–47] || IVOR3[48–59] || 0b0000

Table 129.

Instruction storage interrupt register settings (continued)

Setting description

Table 130.

External input interrupt register settings

Setting description

SRR0

Set to the effective address of the instruction the processor would attempt to execute next

if no exception were present.

SRR1

Set to the contents of the MSR at the time of the interrupt

MSR

UCLE

SPE

—

FE0

—

FE1

ESR

Unchanged

MCSR

Unchanged

DEAR

Unchanged

Vector

IVPR[32–47] || IVOR4[48–59] || 0b0000

IVPR[32–47] ||

p_voffset[0:11] || 0b0000 (non-autovectored)

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